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Paul Mackerras 83816cb9e3 core: Implement BCD Assist instructions addg6s, cdtbcd, cbcdtod ... To avoid adding too much logic, this moves the adder used by OP_ADD out of the case statement in execute1.vhdl so that the result can be used by OP_ADDG6S as well. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		4 years ago
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fmt_log	core: Implement BCD Assist instructions addg6s, cdtbcd, cbcdtod	4 years ago
mw_debug	Add core logging	5 years ago
bin2hex.py	bin2hex: Make sure to generate little endian files	5 years ago
dependencies.py	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	5 years ago
gen_icache_tb.py	icache_tb: Improve test and include test file	5 years ago
run_test.sh	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
run_test_console.sh	Add test cases for new exceptions and supervisor state	5 years ago
test_micropython.py	Update micropython	5 years ago
test_micropython_long.py	Update micropython	5 years ago
vhdltags	Add VHDL TAGS	5 years ago