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120 lines
3.9 KiB
VHDL
120 lines
3.9 KiB
VHDL
library vunit_lib;
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context vunit_lib.vunit_context;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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entity countbits_tb is
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generic (runner_cfg : string := runner_cfg_default);
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end countbits_tb;
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architecture behave of countbits_tb is
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constant clk_period: time := 10 ns;
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signal rs: std_ulogic_vector(63 downto 0);
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signal is_32bit, count_right: std_ulogic := '0';
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signal res: std_ulogic_vector(63 downto 0);
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signal clk: std_ulogic;
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begin
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bitcounter_0: entity work.bit_counter
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port map (
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clk => clk,
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stall => '0',
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rs => rs,
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result => res,
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count_right => count_right,
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is_32bit => is_32bit,
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do_popcnt => '0',
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datalen => "0000"
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable r: std_ulogic_vector(63 downto 0);
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variable rnd : RandomPType;
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begin
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rnd.InitSeed(stim_process'path_name);
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test_runner_setup(runner, runner_cfg);
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while test_suite loop
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if run("Test with input = 0") then
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rs <= (others => '0');
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is_32bit <= '0';
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count_right <= '0';
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wait for clk_period;
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check_equal(res, 16#40#, result("for cntlzd"));
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count_right <= '1';
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wait for clk_period;
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check_equal(res, 16#40#, result("for cnttzd"));
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is_32bit <= '1';
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count_right <= '0';
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wait for clk_period;
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check_equal(res, 16#20#, result("for cntlzw"));
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count_right <= '1';
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wait for clk_period;
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check_equal(res, 16#20#, result("for cnttzw"));
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elsif run("Test cntlzd/w") then
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count_right <= '0';
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for j in 0 to 100 loop
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r := rnd.RandSlv(64);
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r(63) := '1';
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for i in 0 to 63 loop
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rs <= r;
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is_32bit <= '0';
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wait for clk_period;
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check_equal(res, i, result("for cntlzd " & to_hstring(rs)));
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rs <= r(31 downto 0) & r(63 downto 32);
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is_32bit <= '1';
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wait for clk_period;
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if i < 32 then
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check_equal(res, i, result("for cntlzw " & to_hstring(rs)));
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else
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check_equal(res, 32, result("for cntlzw " & to_hstring(rs)));
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end if;
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r := '0' & r(63 downto 1);
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end loop;
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end loop;
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elsif run("Test cnttzd/w") then
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count_right <= '1';
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for j in 0 to 100 loop
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r := rnd.RandSlv(64);
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r(0) := '1';
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for i in 0 to 63 loop
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rs <= r;
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is_32bit <= '0';
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wait for clk_period;
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check_equal(res, i, result("for cnttzd " & to_hstring(rs)));
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is_32bit <= '1';
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wait for clk_period;
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if i < 32 then
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check_equal(res, i, result("for cnttzw " & to_hstring(rs)));
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else
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check_equal(res, 32, result("for cnttzw " & to_hstring(rs)));
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end if;
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r := r(62 downto 0) & '0';
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end loop;
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end loop;
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end if;
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end loop;
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test_runner_cleanup(runner);
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end process;
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end behave;
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