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Michael Neuling
5aaa63ee3b
Means we can synthesize at 40Mhz (where we currently make timing) and our UART still works at 115200 baud. Tested working hello world unmodified with ECP5 eval board. Orange Crab is updated but is untested. Signed-off-by: Michael Neuling <mikey@neuling.org> |
5 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| arty_a7.xdc | 5 years ago | |
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | 5 years ago | |
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| hello_world.hex | ||
| main_bram.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-arty.vhdl | 5 years ago | |
| top-generic.vhdl | 5 years ago | |
| top-nexys-video.vhdl | 5 years ago | |