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Anton Blanchard 9747879643 Add a simple test case ... We use 2 32bit RAMs, so we need to split the test case into two files.		4 years ago
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fmt_log	core: Add framework for an FPU	4 years ago
mw_debug	Add core logging	4 years ago
bin2hex-split.py	Add a simple test case	4 years ago
bin2hex.py	bin2hex: Make sure to generate little endian files	5 years ago
dependencies.py	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	4 years ago
gen_icache_tb.py	icache_tb: Improve test and include test file	5 years ago
run_test.sh	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
run_test_console.sh	Add test cases for new exceptions and supervisor state	5 years ago
test_micropython.py	Update micropython	5 years ago
test_micropython_long.py	Update micropython	5 years ago
vhdltags	Add VHDL TAGS	5 years ago