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caravel-mpw7-20221125
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branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
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fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
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nia-debug
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microwatt/litedram/gen-src
History
Benjamin Herrenschmidt 8d64090a68 sw: Add full memory map to .h and use it for litedram .lds 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
sdram_init sw: Add full memory map to .h and use it for litedram .lds 4 years ago
arty.yml litedram: Update to new LiteX/LiteDRAM version 4 years ago
generate.py litedram: Update to new LiteX/LiteDRAM version 4 years ago
nexys-video.yml litedram: Update to new LiteX/LiteDRAM version 4 years ago
wrapper-mw-init.vhdl litedram: Forward system reset signal 4 years ago
wrapper-self-init.vhdl litedram: Update to new LiteX/LiteDRAM version 4 years ago