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				@ -119,8 +119,6 @@ architecture behaviour of litedram_wrapper is
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				    signal ad3                          : std_ulogic;
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				    signal dram_user_reset              : std_ulogic;
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				    signal wb_ctrl_adr                  : std_ulogic_vector(29 downto 0);
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				    signal wb_ctrl_dat_w                : std_ulogic_vector(31 downto 0);
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				    signal wb_ctrl_dat_r                : std_ulogic_vector(31 downto 0);
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				@ -234,7 +232,6 @@ begin
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				    -- Reset ignored, the reset controller use the pll lock signal,
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				    -- and alternate core reset address set when DRAM is not initialized.
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				    --
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				    system_reset <= '0';
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				    core_alt_reset <= not init_done;
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				    -- State machine
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				@ -242,7 +239,7 @@ begin
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				    begin
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					if rising_edge(system_clk) then
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					    if dram_user_reset = '1' then
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					    if system_reset = '1' then
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						state <= CMD;
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					    else
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						case state is
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				@ -286,7 +283,7 @@ begin
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					    init_done => init_done,
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					    init_error => init_error,
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					    user_clk => system_clk,
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					    user_rst => dram_user_reset,
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					    user_rst => system_reset,
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				            wb_ctrl_adr => wb_ctrl_adr,
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				            wb_ctrl_dat_w => wb_ctrl_dat_w,
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				            wb_ctrl_dat_r => wb_ctrl_dat_r,
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