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6be3e1a336
An extra uart is added at 0xc0008000 attached to valentyusb, using the OrangeCrab's onboard USB port. This has a liteuart interface, an identifier bit is added to syscon. Generated from branch hw_cdc_eptri of https://github.com/litex-hub/valentyusb The generate script is based on valentyusb/sim/generate_verilog.py UARTUSB: usbserial@8000 { device_type = "serial"; compatible = "litex,liteuart"; reg = <0x8000 0x100>; interrupts = <0x15 0x1>; }; (requires extra kernel patches for early console at present v5.16) Signed-off-by: Matt Johnston <matt@codeconstruct.com.au> |
4 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | ||
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | 4 years ago | |
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| fpga-random.vhdl | ||
| fpga-random.xdc | ||
| genesys2.xdc | ||
| hello_world.hex | ||
| main_bram.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | 4 years ago | |
| top-arty.vhdl | 4 years ago | |
| top-generic.vhdl | ||
| top-genesys2.vhdl | 4 years ago | |
| top-nexys-video.vhdl | 4 years ago | |
| top-orangecrab0.2.vhdl | 4 years ago | |
| top-wukong-v2.vhdl | 4 years ago | |
| wukong-v2.xdc | ||