valentyusb: Add USB UART to SOC and OrangeCrab
An extra uart is added at 0xc0008000 attached to valentyusb, using the OrangeCrab's onboard USB port. This has a liteuart interface, an identifier bit is added to syscon. Generated from branch hw_cdc_eptri of https://github.com/litex-hub/valentyusb The generate script is based on valentyusb/sim/generate_verilog.py UARTUSB: usbserial@8000 { device_type = "serial"; compatible = "litex,liteuart"; reg = <0x8000 0x100>; interrupts = <0x15 0x1>; }; (requires extra kernel patches for early console at present v5.16) Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>pull/347/head
Matt Johnston
2 years ago
parent
f57e206841
commit
6be3e1a336
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#!/usr/bin/env python3
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# Based on valentyusb/sim/generate_verilog.py , modified
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# for Microwatt
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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LX_DEPENDENCIES = []
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# Import lxbuildenv to integrate the deps/ directory
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#import lxbuildenv
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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import argparse
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import os
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import yaml
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#from migen import *
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from migen import Module, Signal, Instance, ClockDomain, If
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.fhdl.specials import TSTriple
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from migen.fhdl.bitcontainer import bits_for
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from migen.fhdl.structure import ClockSignal, ResetSignal, Replicate, Cat
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# from litex.build.sim.platform import SimPlatform
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from litex.build.lattice import LatticePlatform
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from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.builder import Builder
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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from valentyusb import usbcore
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import dummyusb, cdc_eptri, eptri, epfifo
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from valentyusb.usbcore.endpoint import EndpointType
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_connectors = []
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class _CRG(Module):
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def __init__(self, platform):
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clk = platform.request("clk")
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rst = platform.request("reset")
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clk12 = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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self.clock_domains.cd_usb_48_to_12 = ClockDomain()
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clk48 = clk.clk48
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self.comb += self.cd_usb_48.clk.eq(clk48)
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self.comb += self.cd_usb_48_to_12.clk.eq(clk48)
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clk12_counter = Signal(2)
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self.sync.usb_48_to_12 += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12.eq(clk12_counter[1])
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self.comb += self.cd_sys.clk.eq(clk.clksys)
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self.comb += self.cd_usb_12.clk.eq(clk12)
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self.comb += [
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ResetSignal("sys").eq(rst),
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ResetSignal("usb_12").eq(rst),
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ResetSignal("usb_48").eq(rst),
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]
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class BaseSoC(SoCCore):
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def __init__(self, platform, io, sys_freq, output_dir="build", usb_variant='dummy', **kwargs):
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# Disable integrated RAM as we'll add it later
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self.integrated_sram_size = 0
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self.output_dir = output_dir
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platform.add_extension(io)
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self.submodules.crg = _CRG(platform)
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# prior to SocCore.__init__
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self.csr_map = {
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"uart": 0, # microwatt soc will remap addresses to 0
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}
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SoCCore.__init__(self, platform, sys_freq,
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cpu_type=None,
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integrated_rom_size=0x0,
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integrated_sram_size=0x0,
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integrated_main_ram_size=0x0,
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csr_address_width=14, csr_data_width=32,
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with_uart=False, with_timer=False)
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# Add USB pads
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usb_pads = platform.request("usb")
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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self.comb += usb_pads.tx_en.eq(usb_iobuf.usb_tx_en)
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if usb_variant == 'eptri':
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self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=True)
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elif usb_variant == 'epfifo':
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self.submodules.usb = epfifo.PerEndpointFifoInterface(usb_iobuf, debug=True)
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elif usb_variant == 'cdc_eptri':
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extra_args = {}
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passthrough = ['product', 'manufacturer']
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for p in passthrough:
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try:
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extra_args[p] = kwargs[p]
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except KeyError:
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pass
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self.submodules.uart = cdc_eptri.CDCUsb(usb_iobuf, debug=True, **extra_args)
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elif usb_variant == 'dummy':
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self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=True)
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else:
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raise ValueError('Invalid endpoints value. It is currently \'eptri\' and \'dummy\'')
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try:
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self.add_wb_master(self.usb.debug_bridge.wishbone)
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except AttributeError:
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pass
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if self.uart:
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self.comb += self.platform.request("interrupt").eq(self.uart.ev.irq)
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wb_ctrl = wishbone.Interface()
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self.add_wb_master(wb_ctrl)
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platform.add_extension(wb_ctrl.get_ios("wb_ctrl"))
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self.comb += wb_ctrl.connect_to_pads(self.platform.request("wishbone"), mode="slave")
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def add_fsm_state_names():
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"""Hack the FSM module to add state names to the output"""
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from migen.fhdl.visit import NodeTransformer
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from migen.genlib.fsm import NextState, NextValue, _target_eq
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from migen.fhdl.bitcontainer import value_bits_sign
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class My_LowerNext(NodeTransformer):
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def __init__(self, next_state_signal, next_state_name_signal, encoding, aliases):
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self.next_state_signal = next_state_signal
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self.next_state_name_signal = next_state_name_signal
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self.encoding = encoding
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self.aliases = aliases
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# (target, next_value_ce, next_value)
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self.registers = []
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def _get_register_control(self, target):
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for x in self.registers:
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if _target_eq(target, x[0]):
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return x[1], x[2]
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raise KeyError
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def visit_unknown(self, node):
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if isinstance(node, NextState):
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try:
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actual_state = self.aliases[node.state]
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except KeyError:
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actual_state = node.state
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return [
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self.next_state_signal.eq(self.encoding[actual_state]),
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self.next_state_name_signal.eq(int.from_bytes(actual_state.encode(), byteorder="big"))
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]
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elif isinstance(node, NextValue):
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try:
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next_value_ce, next_value = self._get_register_control(node.target)
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except KeyError:
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related = node.target if isinstance(node.target, Signal) else None
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next_value = Signal(bits_sign=value_bits_sign(node.target), related=related)
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next_value_ce = Signal(related=related)
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self.registers.append((node.target, next_value_ce, next_value))
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return next_value.eq(node.value), next_value_ce.eq(1)
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else:
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return node
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import migen.genlib.fsm as fsm
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def my_lower_controls(self):
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self.state_name = Signal(len(max(self.encoding,key=len))*8, reset=int.from_bytes(self.reset_state.encode(), byteorder="big"))
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self.next_state_name = Signal(len(max(self.encoding,key=len))*8, reset=int.from_bytes(self.reset_state.encode(), byteorder="big"))
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self.comb += self.next_state_name.eq(self.state_name)
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self.sync += self.state_name.eq(self.next_state_name)
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return My_LowerNext(self.next_state, self.next_state_name, self.encoding, self.state_aliases)
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fsm.FSM._lower_controls = my_lower_controls
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_io = [
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# Wishbone
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("wishbone", 0,
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Subsignal("adr", Pins(30)),
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Subsignal("dat_r", Pins(32)),
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Subsignal("dat_w", Pins(32)),
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Subsignal("sel", Pins(4)),
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Subsignal("cyc", Pins(1)),
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Subsignal("stb", Pins(1)),
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Subsignal("ack", Pins(1)),
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Subsignal("we", Pins(1)),
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Subsignal("cti", Pins(3)),
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Subsignal("bte", Pins(2)),
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Subsignal("err", Pins(1))
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),
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("usb", 0,
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Subsignal("d_p", Pins(1)),
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Subsignal("d_n", Pins(1)),
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Subsignal("pullup", Pins(1)),
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Subsignal("tx_en", Pins(1)),
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),
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("clk", 0,
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Subsignal("clk48", Pins(1)),
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Subsignal("clksys", Pins(1)),
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),
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("interrupt", 0, Pins(1)),
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("reset", 0, Pins(1)),
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]
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def generate(core_config, output_dir, csr_csv):
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toolchain = core_config["toolchain"]
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if toolchain == "trellis":
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platform = LatticePlatform(core_config["device"], [], toolchain=toolchain)
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else:
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raise ValueError(f"Unknown config toolchain {toolchain}")
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soc = BaseSoC(platform, _io, core_config["sys_freq"],
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usb_variant=core_config["usb_variant"],
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cpu_type=None, cpu_variant=None,
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output_dir=output_dir,
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product=core_config["product"],
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manufacturer="Microwatt")
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builder = Builder(soc, output_dir=output_dir,
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csr_csv=csr_csv,
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compile_software=False)
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vns = builder.build(run=False, build_name='valentyusb')
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soc.do_exit(vns)
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def main():
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parser = argparse.ArgumentParser(description="Build standalone ValentyUSB verilog output")
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# parser.add_argument('variant', metavar='VARIANT',
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# choices=['dummy', 'cdc_eptri', 'eptri', 'epfifo'],
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# default='dummy',
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# help='USB variant. Choices: [%(choices)s] (default: %(default)s)' )
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parser.add_argument('--dir', metavar='DIRECTORY',
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default='build',
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help='Output directory (default: %(default)s)' )
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parser.add_argument('--csr', metavar='CSR',
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default='csr.csv',
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help='csr file (default: %(default)s)')
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parser.add_argument('config', type=argparse.FileType('r'),
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help='Input platform config file')
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args = parser.parse_args()
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core_config = yaml.load(args.config.read(), Loader=yaml.Loader)
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# XXX matt - not sure if this needed, maybe only for sim target?
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# add_fsm_state_names()
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output_dir = args.dir
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generate(core_config, output_dir, args.csr)
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print(
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"""Build complete. Output files:
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{}/gateware/valentyusb.v Source Verilog file.
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""".format(output_dir))
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if __name__ == "__main__":
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main()
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@ -0,0 +1,15 @@
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#!/bin/sh
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# This requires https://github.com/litex-hub/valentyusb branch hw_cdc_eptri
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# Tested with
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# commit 912d8e6dc72d45e092e608ffcaabfeaaa6d4580f
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# Date: Wed Jan 6 09:42:42 2021 +0100
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set -e
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GENSRCDIR=$(dirname $0)
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cd $GENSRCDIR
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for b in orangecrab-85-0.2; do
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./generate.py --dir ../generated/$b $b.yml
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done
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{
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"device": "LFE5U-85F-8MG285C",
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"toolchain": "trellis",
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"usb_variant": "cdc_eptri",
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"sys_freq": 48000000,
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"product": "Microwatt on OrangeCrab",
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}
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@ -0,0 +1,5 @@
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# Autogenerated by LiteX / git: --------
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set -e
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yosys -l valentyusb.rpt valentyusb.ys
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nextpnr-ecp5 --json valentyusb.json --lpf valentyusb.lpf --textcfg valentyusb.config --85k --package CSFBGA285 --speed 8 --timing-allow-fail --seed 1
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ecppack valentyusb.config --svf valentyusb.svf --bit valentyusb.bit --bootaddr 0
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@ -0,0 +1,249 @@
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00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
c2
|
||||
01
|
||||
00
|
||||
00
|
||||
00
|
||||
08
|
||||
@ -0,0 +1,118 @@
|
||||
BLOCK RESETPATHS;
|
||||
BLOCK ASYNCPATHS;
|
||||
LOCATE COMP "clk_clk48" SITE "X";
|
||||
LOCATE COMP "clk_clksys" SITE "X";
|
||||
LOCATE COMP "reset" SITE "X";
|
||||
LOCATE COMP "usb_d_p" SITE "X";
|
||||
LOCATE COMP "usb_d_n" SITE "X";
|
||||
LOCATE COMP "usb_pullup" SITE "X";
|
||||
LOCATE COMP "usb_tx_en" SITE "X";
|
||||
LOCATE COMP "interrupt" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[3]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[4]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[5]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[6]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[7]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[8]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[9]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[10]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[11]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[12]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[13]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[14]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[15]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[16]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[17]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[18]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[19]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[20]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[21]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[22]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[23]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[24]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[25]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[26]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[27]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[28]" SITE "X";
|
||||
LOCATE COMP "wishbone_adr[29]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[3]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[4]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[5]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[6]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[7]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[8]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[9]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[10]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[11]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[12]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[13]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[14]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[15]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[16]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[17]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[18]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[19]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[20]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[21]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[22]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[23]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[24]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[25]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[26]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[27]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[28]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[29]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[30]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_r[31]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[3]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[4]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[5]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[6]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[7]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[8]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[9]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[10]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[11]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[12]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[13]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[14]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[15]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[16]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[17]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[18]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[19]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[20]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[21]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[22]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[23]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[24]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[25]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[26]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[27]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[28]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[29]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[30]" SITE "X";
|
||||
LOCATE COMP "wishbone_dat_w[31]" SITE "X";
|
||||
LOCATE COMP "wishbone_sel[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_sel[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_sel[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_sel[3]" SITE "X";
|
||||
LOCATE COMP "wishbone_cyc" SITE "X";
|
||||
LOCATE COMP "wishbone_stb" SITE "X";
|
||||
LOCATE COMP "wishbone_ack" SITE "X";
|
||||
LOCATE COMP "wishbone_we" SITE "X";
|
||||
LOCATE COMP "wishbone_cti[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_cti[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_cti[2]" SITE "X";
|
||||
LOCATE COMP "wishbone_bte[0]" SITE "X";
|
||||
LOCATE COMP "wishbone_bte[1]" SITE "X";
|
||||
LOCATE COMP "wishbone_err" SITE "X";
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,6 @@
|
||||
verilog_defaults -push
|
||||
verilog_defaults -add -defer
|
||||
read_verilog /home/matt/3rd/fpga/microwatt/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v
|
||||
verilog_defaults -pop
|
||||
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
|
||||
synth_ecp5 -json valentyusb.json -top valentyusb
|
||||
@ -0,0 +1,232 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11
|
||||
//--------------------------------------------------------------------------------
|
||||
#include <generated/soc.h>
|
||||
#ifndef __GENERATED_CSR_H
|
||||
#define __GENERATED_CSR_H
|
||||
#include <stdint.h>
|
||||
#include <system.h>
|
||||
#ifndef CSR_ACCESSORS_DEFINED
|
||||
#include <hw/common.h>
|
||||
#endif /* ! CSR_ACCESSORS_DEFINED */
|
||||
#ifndef CSR_BASE
|
||||
#define CSR_BASE 0x0L
|
||||
#endif
|
||||
|
||||
/* uart */
|
||||
#define CSR_UART_BASE (CSR_BASE + 0x0L)
|
||||
#define CSR_UART_RXTX_ADDR (CSR_BASE + 0x0L)
|
||||
#define CSR_UART_RXTX_SIZE 1
|
||||
static inline uint32_t uart_rxtx_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x0L);
|
||||
}
|
||||
static inline void uart_rxtx_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x0L);
|
||||
}
|
||||
#define CSR_UART_TXFULL_ADDR (CSR_BASE + 0x4L)
|
||||
#define CSR_UART_TXFULL_SIZE 1
|
||||
static inline uint32_t uart_txfull_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x4L);
|
||||
}
|
||||
#define CSR_UART_RXEMPTY_ADDR (CSR_BASE + 0x8L)
|
||||
#define CSR_UART_RXEMPTY_SIZE 1
|
||||
static inline uint32_t uart_rxempty_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x8L);
|
||||
}
|
||||
#define CSR_UART_EV_STATUS_ADDR (CSR_BASE + 0xcL)
|
||||
#define CSR_UART_EV_STATUS_SIZE 1
|
||||
static inline uint32_t uart_ev_status_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0xcL);
|
||||
}
|
||||
#define CSR_UART_EV_STATUS_TX_OFFSET 0
|
||||
#define CSR_UART_EV_STATUS_TX_SIZE 1
|
||||
static inline uint32_t uart_ev_status_tx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 0) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_status_tx_read(void) {
|
||||
uint32_t word = uart_ev_status_read();
|
||||
return uart_ev_status_tx_extract(word);
|
||||
}
|
||||
#define CSR_UART_EV_STATUS_RX_OFFSET 1
|
||||
#define CSR_UART_EV_STATUS_RX_SIZE 1
|
||||
static inline uint32_t uart_ev_status_rx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 1) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_status_rx_read(void) {
|
||||
uint32_t word = uart_ev_status_read();
|
||||
return uart_ev_status_rx_extract(word);
|
||||
}
|
||||
#define CSR_UART_EV_PENDING_ADDR (CSR_BASE + 0x10L)
|
||||
#define CSR_UART_EV_PENDING_SIZE 1
|
||||
static inline uint32_t uart_ev_pending_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x10L);
|
||||
}
|
||||
static inline void uart_ev_pending_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x10L);
|
||||
}
|
||||
#define CSR_UART_EV_PENDING_TX_OFFSET 0
|
||||
#define CSR_UART_EV_PENDING_TX_SIZE 1
|
||||
static inline uint32_t uart_ev_pending_tx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 0) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_pending_tx_read(void) {
|
||||
uint32_t word = uart_ev_pending_read();
|
||||
return uart_ev_pending_tx_extract(word);
|
||||
}
|
||||
static inline uint32_t uart_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
|
||||
}
|
||||
static inline void uart_ev_pending_tx_write(uint32_t plain_value) {
|
||||
uint32_t oldword = uart_ev_pending_read();
|
||||
uint32_t newword = uart_ev_pending_tx_replace(oldword, plain_value);
|
||||
uart_ev_pending_write(newword);
|
||||
}
|
||||
#define CSR_UART_EV_PENDING_RX_OFFSET 1
|
||||
#define CSR_UART_EV_PENDING_RX_SIZE 1
|
||||
static inline uint32_t uart_ev_pending_rx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 1) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_pending_rx_read(void) {
|
||||
uint32_t word = uart_ev_pending_read();
|
||||
return uart_ev_pending_rx_extract(word);
|
||||
}
|
||||
static inline uint32_t uart_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
|
||||
}
|
||||
static inline void uart_ev_pending_rx_write(uint32_t plain_value) {
|
||||
uint32_t oldword = uart_ev_pending_read();
|
||||
uint32_t newword = uart_ev_pending_rx_replace(oldword, plain_value);
|
||||
uart_ev_pending_write(newword);
|
||||
}
|
||||
#define CSR_UART_EV_ENABLE_ADDR (CSR_BASE + 0x14L)
|
||||
#define CSR_UART_EV_ENABLE_SIZE 1
|
||||
static inline uint32_t uart_ev_enable_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x14L);
|
||||
}
|
||||
static inline void uart_ev_enable_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x14L);
|
||||
}
|
||||
#define CSR_UART_EV_ENABLE_TX_OFFSET 0
|
||||
#define CSR_UART_EV_ENABLE_TX_SIZE 1
|
||||
static inline uint32_t uart_ev_enable_tx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 0) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_enable_tx_read(void) {
|
||||
uint32_t word = uart_ev_enable_read();
|
||||
return uart_ev_enable_tx_extract(word);
|
||||
}
|
||||
static inline uint32_t uart_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
|
||||
}
|
||||
static inline void uart_ev_enable_tx_write(uint32_t plain_value) {
|
||||
uint32_t oldword = uart_ev_enable_read();
|
||||
uint32_t newword = uart_ev_enable_tx_replace(oldword, plain_value);
|
||||
uart_ev_enable_write(newword);
|
||||
}
|
||||
#define CSR_UART_EV_ENABLE_RX_OFFSET 1
|
||||
#define CSR_UART_EV_ENABLE_RX_SIZE 1
|
||||
static inline uint32_t uart_ev_enable_rx_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 1) & mask );
|
||||
}
|
||||
static inline uint32_t uart_ev_enable_rx_read(void) {
|
||||
uint32_t word = uart_ev_enable_read();
|
||||
return uart_ev_enable_rx_extract(word);
|
||||
}
|
||||
static inline uint32_t uart_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
|
||||
}
|
||||
static inline void uart_ev_enable_rx_write(uint32_t plain_value) {
|
||||
uint32_t oldword = uart_ev_enable_read();
|
||||
uint32_t newword = uart_ev_enable_rx_replace(oldword, plain_value);
|
||||
uart_ev_enable_write(newword);
|
||||
}
|
||||
#define CSR_UART_TUNING_WORD_ADDR (CSR_BASE + 0x18L)
|
||||
#define CSR_UART_TUNING_WORD_SIZE 1
|
||||
static inline uint32_t uart_tuning_word_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x18L);
|
||||
}
|
||||
static inline void uart_tuning_word_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x18L);
|
||||
}
|
||||
#define CSR_UART_CONFIGURED_ADDR (CSR_BASE + 0x1cL)
|
||||
#define CSR_UART_CONFIGURED_SIZE 1
|
||||
static inline uint32_t uart_configured_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x1cL);
|
||||
}
|
||||
static inline void uart_configured_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x1cL);
|
||||
}
|
||||
|
||||
/* ctrl */
|
||||
#define CSR_CTRL_BASE (CSR_BASE + 0x800L)
|
||||
#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x800L)
|
||||
#define CSR_CTRL_RESET_SIZE 1
|
||||
static inline uint32_t ctrl_reset_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x800L);
|
||||
}
|
||||
static inline void ctrl_reset_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x800L);
|
||||
}
|
||||
#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
|
||||
#define CSR_CTRL_RESET_SOC_RST_SIZE 1
|
||||
static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 0) & mask );
|
||||
}
|
||||
static inline uint32_t ctrl_reset_soc_rst_read(void) {
|
||||
uint32_t word = ctrl_reset_read();
|
||||
return ctrl_reset_soc_rst_extract(word);
|
||||
}
|
||||
static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
|
||||
}
|
||||
static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
|
||||
uint32_t oldword = ctrl_reset_read();
|
||||
uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
|
||||
ctrl_reset_write(newword);
|
||||
}
|
||||
#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
|
||||
#define CSR_CTRL_RESET_CPU_RST_SIZE 1
|
||||
static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return ( (oldword >> 1) & mask );
|
||||
}
|
||||
static inline uint32_t ctrl_reset_cpu_rst_read(void) {
|
||||
uint32_t word = ctrl_reset_read();
|
||||
return ctrl_reset_cpu_rst_extract(word);
|
||||
}
|
||||
static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
|
||||
uint32_t mask = ((1 << 1)-1);
|
||||
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
|
||||
}
|
||||
static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
|
||||
uint32_t oldword = ctrl_reset_read();
|
||||
uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
|
||||
ctrl_reset_write(newword);
|
||||
}
|
||||
#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x804L)
|
||||
#define CSR_CTRL_SCRATCH_SIZE 1
|
||||
static inline uint32_t ctrl_scratch_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x804L);
|
||||
}
|
||||
static inline void ctrl_scratch_write(uint32_t v) {
|
||||
csr_write_simple(v, CSR_BASE + 0x804L);
|
||||
}
|
||||
#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x808L)
|
||||
#define CSR_CTRL_BUS_ERRORS_SIZE 1
|
||||
static inline uint32_t ctrl_bus_errors_read(void) {
|
||||
return csr_read_simple(CSR_BASE + 0x808L);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,9 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11
|
||||
//--------------------------------------------------------------------------------
|
||||
#ifndef __GENERATED_GIT_H
|
||||
#define __GENERATED_GIT_H
|
||||
|
||||
#define MIGEN_GIT_SHA1 "--------"
|
||||
#define LITEX_GIT_SHA1 "--------"
|
||||
#endif
|
||||
@ -0,0 +1,15 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11
|
||||
//--------------------------------------------------------------------------------
|
||||
#ifndef __GENERATED_MEM_H
|
||||
#define __GENERATED_MEM_H
|
||||
|
||||
#ifndef CSR_BASE
|
||||
#define CSR_BASE 0x00000000L
|
||||
#define CSR_SIZE 0x00010000
|
||||
#endif
|
||||
|
||||
#ifndef MEM_REGIONS
|
||||
#define MEM_REGIONS "CSR 0x00000000 0x10000 "
|
||||
#endif
|
||||
#endif
|
||||
@ -0,0 +1,40 @@
|
||||
//--------------------------------------------------------------------------------
|
||||
// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11
|
||||
//--------------------------------------------------------------------------------
|
||||
#ifndef __GENERATED_SOC_H
|
||||
#define __GENERATED_SOC_H
|
||||
#define CONFIG_CLOCK_FREQUENCY 48000000
|
||||
#define CONFIG_CPU_TYPE_NONE
|
||||
#define CONFIG_CPU_VARIANT_STANDARD
|
||||
#define CONFIG_CPU_HUMAN_NAME "Unknown"
|
||||
#define CONFIG_CSR_DATA_WIDTH 32
|
||||
#define CONFIG_CSR_ALIGNMENT 32
|
||||
#define CONFIG_BUS_STANDARD "WISHBONE"
|
||||
#define CONFIG_BUS_DATA_WIDTH 32
|
||||
#define CONFIG_BUS_ADDRESS_WIDTH 32
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
static inline int config_clock_frequency_read(void) {
|
||||
return 48000000;
|
||||
}
|
||||
static inline const char * config_cpu_human_name_read(void) {
|
||||
return "Unknown";
|
||||
}
|
||||
static inline int config_csr_data_width_read(void) {
|
||||
return 32;
|
||||
}
|
||||
static inline int config_csr_alignment_read(void) {
|
||||
return 32;
|
||||
}
|
||||
static inline const char * config_bus_standard_read(void) {
|
||||
return "WISHBONE";
|
||||
}
|
||||
static inline int config_bus_data_width_read(void) {
|
||||
return 32;
|
||||
}
|
||||
static inline int config_bus_address_width_read(void) {
|
||||
return 32;
|
||||
}
|
||||
#endif // !__ASSEMBLER__
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue