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6fe077910b
This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
|---|---|---|
| .. | ||
| VexRiscv.v | 6 years ago | |
| fusesoc-add-files.py | 5 years ago | |
| sim_dram_verilate.mk | 5 years ago | |
| sim_litedram.vhdl | 5 years ago | |
| sim_litedram_c.cpp | 5 years ago | |
| wrapper-mw-init.vhdl | 5 years ago | |
| wrapper-self-init.vhdl | 5 years ago | |