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Paul Mackerras
2be2440734
This adds, as comments, lines which would if uncommented define properties which associate the pins of the headers on the Arty A7 board with FPGA pins. It also adds properties for LEDs 1--3, also commented out for now. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
4 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| acorn-cle-215.xdc | ||
| arty_a7.xdc | 4 years ago | |
| clk_gen_bypass.vhd | ||
| clk_gen_ecp5.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| fpga-random.vhdl | ||
| fpga-random.xdc | ||
| genesys2.xdc | 4 years ago | |
| hello_world.hex | ||
| main_bram.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-acorn-cle-215.vhdl | ||
| top-arty.vhdl | 4 years ago | |
| top-generic.vhdl | 4 years ago | |
| top-genesys2.vhdl | 4 years ago | |
| top-nexys-video.vhdl | 4 years ago | |