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Paul Mackerras
78de4fef72
This plumbs the LOG_LENGTH parameter (which controls how many entries the core log RAM has) up to the top level so that it can be set on the fusesoc command line and have different default values on different FPGAs. It now defaults to 512 entries generally and on the Artix-7 35 parts, and 2048 on the larger Artix-7 FPGAs. It can be set to 0 if desired. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
5 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| arty_a7.xdc | 5 years ago | |
| clk_gen_bypass.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| hello_world.hex | ||
| main_bram.vhdl | ||
| nexys-video.xdc | 5 years ago | |
| nexys_a7.xdc | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | 5 years ago | |
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-arty.vhdl | 5 years ago | |
| top-generic.vhdl | 5 years ago | |
| top-nexys-video.vhdl | 5 years ago | |