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Joel Stanley 60e5f7b958 spi: Fix dat_i_l constraints ... No cells matched 'get_cells -hierarchical -filter {NAME =~*/spi_rxtx/dat_i_l*}'. [build/microwatt_0/src/microwatt_0/fpga/arty_a7.xdc:42] The signal is in it's own process so the net name ends up being spi_rxtx/input_delay_1.dat_i_l_reg. After this change the log shows: Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42). Signed-off-by: Joel Stanley <joel@jms.id.au>		5 years ago
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LICENSE	Initial import of microwatt	5 years ago
arty_a7.xdc	spi: Fix dat_i_l constraints	5 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	5 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	5 years ago
cmod_a7-35.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	hello_world: Use new headers and frequency from syscon	5 years ago
main_bram.vhdl	Fix some ghdlsynth issues with fpga_bram	5 years ago
nexys-video.xdc	spi: Add SPI Flash controller	5 years ago
nexys_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
pp_fifo.vhd	pp_fifo: Fix full fifo losing all data on simultaneous push & pop	5 years ago
pp_soc_uart.vhd	uart: Remove combinational loops on ack and stall signal	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc_reset.vhdl	soc_reset: Use counters, add synchronizers	5 years ago
soc_reset_tb.vhdl	Exit cleanly from testbench on success	5 years ago
top-arty.vhdl	Merge pull request #208 from paulusmack/faster	5 years ago
top-generic.vhdl	soc: Don't require dram wishbones signals to be wired by toplevel	5 years ago
top-nexys-video.vhdl	soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding	5 years ago