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microwatt
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master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/fpga
History
Olof Kindgren abca85b034 Add constraint file for Nexys A7 5 years ago
..
LICENSE
…
clk_gen_bypass.vhd Add dummy clock generator 5 years ago
firmware.hex Add a few more FPGA related files 5 years ago
nexys-video.xdc
…
nexys_a7.xdc Add constraint file for Nexys A7 5 years ago
nodivide.patch Add a few more FPGA related files 5 years ago
pp_fifo.vhd
…
pp_soc_memory.vhd Expose ram init file and memory size through toplevel 5 years ago
pp_soc_reset.vhd
…
pp_soc_uart.vhd
…
pp_utilities.vhd
…
toplevel.vhd Expose ram init file and memory size through toplevel 5 years ago