You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
8e0389b973
This replaces the simple_ram_behavioural and mw_soc_memory modules with a common wishbone_bram_wrapper.vhdl that interfaces the pipelined WB with a lower-level RAM module, along with an FPGA and a sim variants of the latter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
|---|---|---|
| .. | ||
| mw_debug | ||
| dependencies.py | ||
| gen_icache_tb.py | ||
| hash.py | ||
| run_test.sh | 5 years ago | |
| test_micropython.py | 5 years ago | |
| test_micropython_long.py | 5 years ago | |
| verific.sh | ||