microwatt/fpga
Benjamin Herrenschmidt b0241d9f2d corefile/nexys_video: Parameter fixes
This fixes up a few issues with parameters:

Only arty has "has_uart1" since we haven't added plumbing for a second UART
anywhere else. Also "uart_is_16550" was mixing on one of the nexys_video
targets, and nexys_video toplevel was missing LOG_LENGTH.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
..
LICENSE Initial import of microwatt
arty_a7.xdc uart: Import and hook up opencore 16550 compatible UART
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_ecp5.vhd Add PLL for ECP5 device
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration
cmod_a7-35.xdc Add SPI configuration to Xilinx constraint files
firmware.hex Add a few more FPGA related files
hello_world.hex hello_world: Use new headers and frequency from syscon
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram
nexys-video.xdc spi: Add SPI Flash controller
nexys_a7.xdc Add SPI configuration to Xilinx constraint files
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal
pp_utilities.vhd Initial import of microwatt
soc_reset.vhdl soc_reset: Use counters, add synchronizers
soc_reset_tb.vhdl Exit cleanly from testbench on success
top-arty.vhdl uart: Make 16550 the default
top-generic.vhdl uart: Make 16550 the default
top-nexys-video.vhdl corefile/nexys_video: Parameter fixes