A tiny Open POWER ISA softcore written in VHDL 2008
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Benjamin Herrenschmidt 472d8f94a2 wb_arbiter: Avoid IDLE cycle when not changing master
Consecutive accesses from the same master shouldn't need an IDLE
cycle. Completely remove the IDLE state and switch master when
the bus is idle, but stay on the last selected one between cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
fpga ram: Rework main RAM interface 4 years ago
hello_world Rebuild hello world assuming a 50MHz clock 5 years ago
media Add title image 4 years ago
scripts ram: Rework main RAM interface 4 years ago
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 5 years ago
tests Initial import of microwatt 5 years ago
.gitignore Update gitignore for new test bench build files 4 years ago
.travis.yml Allow a full make check on Travis 5 years ago
LICENSE Initial import of microwatt 5 years ago
Makefile ram: Rework main RAM interface 4 years ago
README.md ram: Rework main RAM interface 4 years ago
cache_ram.vhdl dcache: Introduce an extra cycle latency to make timing 4 years ago
common.vhdl dcache: Add a dcache 4 years ago
control.vhdl Add CR hazard detection 4 years ago
core.vhdl Add option to not flatten hierarchy 4 years ago
core_debug.vhdl fetch/icache: Fit icache in BRAM 4 years ago
core_tb.vhdl ram: Rework main RAM interface 4 years ago
countzero.vhdl countzero: Reorganize to have fewer levels of logic and fewer LUTs 4 years ago
countzero_tb.vhdl countzero: Add a testbench 4 years ago
cr_file.vhdl Reformat CR file 5 years ago
cr_hazard.vhdl Add CR hazard detection 4 years ago
crhelpers.vhdl crhelpers: Constraint "crnum" integer 4 years ago
dcache.vhdl Move log2/ispow2 to a utils package 4 years ago
dcache_tb.vhdl ram: Rework main RAM interface 4 years ago
decode1.vhdl insn: Simplistic implementation of icbi 4 years ago
decode2.vhdl Do sign-extension instructions in writeback instead of execute1 4 years ago
decode_types.vhdl decode: Reformat decode_types.vhdl 4 years ago
divider.vhdl writeback: Do data formatting and condition recording in writeback 4 years ago
divider_tb.vhdl writeback: Do data formatting and condition recording in writeback 4 years ago
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl 5 years ago
dmi_dtm_tb.vhdl ram: Rework main RAM interface 4 years ago
dmi_dtm_xilinx.vhdl Don't reset JTAG request register asynchronously 4 years ago
execute1.vhdl Merge pull request #113 from mikey/exec-sim-remove 4 years ago
fetch1.vhdl fetch/icache: Fit icache in BRAM 4 years ago
fetch2.vhdl fetch2: Remove blank line 4 years ago
glibc_random.vhdl Reformat glibc_random 5 years ago
glibc_random_helpers.vhdl Reformat glibc_random 5 years ago
gpr_hazard.vhdl Add GPR hazard detection 4 years ago
helpers.vhdl Reformat helpers 5 years ago
icache.vhdl Move log2/ispow2 to a utils package 4 years ago
icache_tb.vhdl ram: Rework main RAM interface 4 years ago
icache_test.bin icache_tb: Improve test and include test file 4 years ago
insn_helpers.vhdl Add MCRF instruction 4 years ago
loadstore1.vhdl dcache: Add a dcache 4 years ago
logical.vhdl Consolidate logical instructions 4 years ago
microwatt.core ram: Rework main RAM interface 4 years ago
multiply.vhdl writeback: Do data formatting and condition recording in writeback 4 years ago
multiply_tb.vhdl writeback: Do data formatting and condition recording in writeback 4 years ago
plru.vhdl plru: Improve sensitivity list 4 years ago
plru_tb.vhdl plru: Add a simple PLRU module 4 years ago
ppc_fx_insns.vhdl Implement absolute branches 4 years ago
register_file.vhdl Fix register file size (there are 32 gprs). 4 years ago
rotator.vhdl Add a rotate/mask/shift unit and use it in execute1 4 years ago
rotator_tb.vhdl Add a rotate/mask/shift unit and use it in execute1 4 years ago
sim_bram.vhdl ram: Rework main RAM interface 4 years ago
sim_bram_helpers.vhdl ram: Rework main RAM interface 4 years ago
sim_bram_helpers_c.c ram: Rework main RAM interface 4 years ago
sim_console.vhdl Reformat sim_console 5 years ago
sim_console_c.c Make sim poll non-blocking 5 years ago
sim_jtag.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket_c.c debug/sim: Make connect/disconnect messages quieter 4 years ago
sim_uart.vhdl Share soc.vhdl between FPGA and sim 5 years ago
soc.vhdl ram: Rework main RAM interface 4 years ago
utils.vhdl Move log2/ispow2 to a utils package 4 years ago
wishbone_arbiter.vhdl wb_arbiter: Avoid IDLE cycle when not changing master 4 years ago
wishbone_bram_tb.bin ram: Rework main RAM interface 4 years ago
wishbone_bram_tb.vhdl ram: Rework main RAM interface 4 years ago
wishbone_bram_wrapper.vhdl ram: Ack stores early 4 years ago
wishbone_debug_master.vhdl wb_debug: Add wishbone pipelining support 4 years ago
wishbone_types.vhdl wishbone: Add stall signal 4 years ago
writeback.vhdl writeback: Slightly improve timing 4 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)