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982cf166dd
This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
|---|---|---|
| .. | ||
| mw_debug | 5 years ago | |
| bin2hex.py | 5 years ago | |
| dependencies.py | 5 years ago | |
| gen_icache_tb.py | 5 years ago | |
| run_test.sh | 5 years ago | |
| run_test_console.sh | 5 years ago | |
| test_micropython.py | 5 years ago | |
| test_micropython_long.py | 5 years ago | |
| verific.sh | 5 years ago | |
| vhdltags | 5 years ago | |