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microwatt/valentyusb/generated/orangecrab-85-0.2
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Matt Johnston 6be3e1a336 valentyusb: Add USB UART to SOC and OrangeCrab 
An extra uart is added at 0xc0008000 attached to valentyusb, using
the OrangeCrab's onboard USB port.
This has a liteuart interface, an identifier bit is added to syscon.

Generated from branch hw_cdc_eptri of
https://github.com/litex-hub/valentyusb

The generate script is based on valentyusb/sim/generate_verilog.py

UARTUSB: usbserial@8000 {
        device_type = "serial";
        compatible = "litex,liteuart";
        reg = <0x8000 0x100>;
        interrupts = <0x15 0x1>;
};

(requires extra kernel patches for early console at present v5.16)

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 		2 years ago
..
gateware valentyusb: Add USB UART to SOC and OrangeCrab 2 years ago
software/include/generated valentyusb: Add USB UART to SOC and OrangeCrab 2 years ago