Paul Mackerras
1c4b5def36
This gets rid of the adder in writeback that computes redirect_nia. Instead, the main adder in the ALU is used to compute the branch target for relative branches. We now decode b and bc differently depending on the AA field, generating INSN_brel, INSN_babs, INSN_bcrel or INSN_bcabs as appropriate. Each one has a separate entry in the decode table in decode1; the *rel versions use CIA as the A input. The bclr/bcctr/bctar and rfid instructions now select ramspr_result for the main result mux to get the redirect address into ex1.e.write_data. For branches which are predicted taken but not actually taken, we need to redirect to the following instruction. We also need to do that for isync. We do this in the execute2 stage since whether or not to do it depends on the branch result. The next_nia computation is moved to the execute2 stage and comes in via a new leg on the secondary result multiplexer, making next_nia available ultimately in ex2.e.write_data. This also means that the next_nia leg of the primary result multiplexer is gone. Incrementing last_nia by 4 for sc (so that SRR0 points to the following instruction) is also moved to execute2. Writing CIA+4 to LR was previously done through the main result multiplexer. Now it comes in explicitly in the ramspr write logic. Overall this removes the br_offset and abs_br fields and the logic to add br_offset and next_nia, and one leg of the primary result multiplexer, at the cost of a few extra control signals between execute1 and execute2 and some multiplexing for the ramspr write side and an extra input on the secondary result multiplexer. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
1 year ago | |
|---|---|---|
| .github/workflows | 2 years ago | |
| constraints | ||
| fpga | 1 year ago | |
| hello_world | 2 years ago | |
| include | 1 year ago | |
| lib | ||
| litedram | 2 years ago | |
| liteeth | ||
| litesdcard | ||
| media | ||
| micropython | ||
| openocd | 2 years ago | |
| rust_lib_demo | ||
| scripts | 1 year ago | |
| sim-unisim | ||
| tests | 1 year ago | |
| uart16550 | 2 years ago | |
| verilator | ||
| .gitignore | 2 years ago | |
| LICENSE | ||
| Makefile | 1 year ago | |
| README.md | ||
| cache_ram.vhdl | ||
| common.vhdl | 1 year ago | |
| control.vhdl | ||
| core.vhdl | 1 year ago | |
| core_debug.vhdl | 1 year ago | |
| core_dram_tb.vhdl | 2 years ago | |
| core_flash_tb.vhdl | ||
| core_tb.vhdl | ||
| countbits.vhdl | ||
| countbits_tb.vhdl | ||
| cr_file.vhdl | ||
| crhelpers.vhdl | ||
| dcache.vhdl | 1 year ago | |
| dcache_tb.vhdl | 2 years ago | |
| decode1.vhdl | 1 year ago | |
| decode2.vhdl | 1 year ago | |
| decode_types.vhdl | 1 year ago | |
| divider.vhdl | ||
| divider_tb.vhdl | ||
| dmi_dtm_dummy.vhdl | ||
| dmi_dtm_ecp5.vhdl | ||
| dmi_dtm_tb.vhdl | ||
| dmi_dtm_xilinx.vhdl | ||
| dram_tb.vhdl | 2 years ago | |
| execute1.vhdl | 1 year ago | |
| fetch1.vhdl | 1 year ago | |
| foreign_random.vhdl | ||
| fpu.vhdl | ||
| git.vhdl.in | 2 years ago | |
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| gpio.vhdl | 2 years ago | |
| helpers.vhdl | ||
| icache.vhdl | 1 year ago | |
| icache_tb.vhdl | ||
| icache_test.bin | ||
| insn_helpers.vhdl | 1 year ago | |
| loadstore1.vhdl | 1 year ago | |
| logical.vhdl | 1 year ago | |
| microwatt.core | 2 years ago | |
| mmu.vhdl | ||
| multiply-32s.vhdl | ||
| multiply.vhdl | ||
| multiply_tb.vhdl | ||
| nonrandom.vhdl | ||
| plru_tb.vhdl | 2 years ago | |
| plrufn.vhdl | 2 years ago | |
| pmu.vhdl | ||
| ppc_fx_insns.vhdl | ||
| predecode.vhdl | 1 year ago | |
| random.vhdl | ||
| register_file.vhdl | ||
| rotator.vhdl | ||
| rotator_tb.vhdl | ||
| run.py | 2 years ago | |
| sim_16550_uart.vhdl | ||
| sim_bram.vhdl | ||
| sim_bram_helpers.vhdl | ||
| sim_bram_helpers_c.c | ||
| sim_console.vhdl | ||
| sim_console_c.c | ||
| sim_jtag.vhdl | ||
| sim_jtag_socket.vhdl | ||
| sim_jtag_socket_c.c | ||
| sim_no_flash.vhdl | ||
| sim_pp_uart.vhdl | ||
| sim_vhpi_c.c | ||
| sim_vhpi_c.h | ||
| soc.vhdl | 2 years ago | |
| spi_flash_ctrl.vhdl | ||
| spi_rxtx.vhdl | ||
| sync_fifo.vhdl | ||
| syscon.vhdl | 2 years ago | |
| utils.vhdl | ||
| wishbone_arbiter.vhdl | ||
| wishbone_bram_tb.bin | ||
| wishbone_bram_tb.vhdl | ||
| wishbone_bram_wrapper.vhdl | ||
| wishbone_debug_master.vhdl | ||
| wishbone_types.vhdl | ||
| writeback.vhdl | 1 year ago | |
| xics.vhdl | ||
| xilinx-mult-32s.vhdl | ||
| xilinx-mult.vhdl | ||
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../
A prebuilt micropython image is also available in the micropython/ directory.
-
Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.
If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
-
Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
To build using Docker:
make DOCKER=1
and to build using Podman:
make PODMAN=1
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
Or if you were using the pre-built image:
ln -s micropython/firmware.bin main_ram.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
Fedora users can get FuseSoC package via
sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
- If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
fusesoc fetch uart16550
fusesoc library add microwatt /path/to/microwatt
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Linux on Microwatt
Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested platform, but it's also been tested on the OrangeCrab and ButterStick.
-
Use buildroot to create a userspace
A small change is required to glibc in order to support the VMX/AltiVec-less Microwatt, as float128 support is mandiatory and for this in GCC requires VSX/AltiVec. This change is included in Joel's buildroot fork, along with a defconfig:
git clone -b microwatt https://github.com/shenki/buildroot cd buildroot make ppc64le_microwatt_defconfig makeThe output is
output/images/rootfs.cpio. -
Build the Linux kernel
git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git cd linux make ARCH=powerpc microwatt_defconfig make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \ CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`The output is
arch/powerpc/boot/dtbImage.microwatt.elf. -
Build gateware using FuseSoC
First configure FuseSoC as above.
fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0The output is
build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit. -
Program the flash
This operation will overwrite the contents of your flash.
For the Arty A7 A100, set
FLASH_ADDRESSto0x400000and pass-f a100.For the Arty A7 A35, set
FLASH_ADDRESSto0x300000and pass-f a35.microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS -
Connect to the second USB TTY device exposed by the FPGA
minicom -D /dev/ttyUSB1The gateware has firmware that will look at
FLASH_ADDRESSand attempt to parse an ELF there, loading it to the address specified in the ELF header and jumping to it.
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
- There are a few instructions still to be implemented:
- Vector/VMX/VSX