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Paul Mackerras 18120f153d MMU: Implement a vestigial partition table 
This implements a 1-entry partition table, so that instead of getting
the process table base address from the PRTBL SPR, the MMU now reads
the doubleword pointed to by the PTCR register plus 8 to get the
process table base address.  The partition table entry is cached.

Having the PTCR and the vestigial partition table reduces the amount
of software change required in Linux for Microwatt support.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
..
decrementer console: Cleanup console API
fpu FPU: Implement floating multiply-add instructions
illegal console: Cleanup console API
misc tests/misc: Add a test for correct CTR and LR updating by branches
mmu MMU: Implement a vestigial partition table
modes MMU: Implement a vestigial partition table
privileged MMU: Implement a vestigial partition table
reservation MMU: Implement a vestigial partition table
sc console: Cleanup console API
spr_read MMU: Implement a vestigial partition table
trace tests/trace: Test trace interrupt vs. FP unavailable interrupt
xics console: Cleanup console API
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893.out Dump CTR, LR and CR on sim termination, and update our tests
894.bin tests: Put an attn instruction at 0x700
894.out Dump CTR, LR and CR on sim termination, and update our tests
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896.out Dump CTR, LR and CR on sim termination, and update our tests
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898.bin tests: Put an attn instruction at 0x700
898.out Dump CTR, LR and CR on sim termination, and update our tests
899.bin tests: Put an attn instruction at 0x700
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900.bin tests: Put an attn instruction at 0x700
900.out Dump CTR, LR and CR on sim termination, and update our tests
901.bin tests: Put an attn instruction at 0x700
901.out Dump CTR, LR and CR on sim termination, and update our tests
902.bin tests: Put an attn instruction at 0x700
902.out Dump CTR, LR and CR on sim termination, and update our tests
903.bin tests: Put an attn instruction at 0x700
903.out Dump CTR, LR and CR on sim termination, and update our tests
904.bin tests: Put an attn instruction at 0x700
904.out Dump CTR, LR and CR on sim termination, and update our tests
905.bin tests: Put an attn instruction at 0x700
905.out Dump CTR, LR and CR on sim termination, and update our tests
906.bin tests: Put an attn instruction at 0x700
906.out Dump CTR, LR and CR on sim termination, and update our tests
907.bin tests: Put an attn instruction at 0x700
907.out Dump CTR, LR and CR on sim termination, and update our tests
908.bin tests: Put an attn instruction at 0x700
908.out Dump CTR, LR and CR on sim termination, and update our tests
909.bin tests: Put an attn instruction at 0x700
909.out Dump CTR, LR and CR on sim termination, and update our tests
910.bin tests: Put an attn instruction at 0x700
910.out Dump CTR, LR and CR on sim termination, and update our tests
911.bin tests: Put an attn instruction at 0x700
911.out Dump CTR, LR and CR on sim termination, and update our tests
912.bin tests: Put an attn instruction at 0x700
912.out Dump CTR, LR and CR on sim termination, and update our tests
913.bin tests: Put an attn instruction at 0x700
913.out Dump CTR, LR and CR on sim termination, and update our tests
914.bin tests: Put an attn instruction at 0x700
914.out Dump CTR, LR and CR on sim termination, and update our tests
915.bin tests: Put an attn instruction at 0x700
915.out Dump CTR, LR and CR on sim termination, and update our tests
916.bin tests: Put an attn instruction at 0x700
916.out Dump CTR, LR and CR on sim termination, and update our tests
917.bin tests: Put an attn instruction at 0x700
917.out Dump CTR, LR and CR on sim termination, and update our tests
918.bin tests: Put an attn instruction at 0x700
918.out Dump CTR, LR and CR on sim termination, and update our tests
919.bin tests: Put an attn instruction at 0x700
919.out Dump CTR, LR and CR on sim termination, and update our tests
920.bin tests: Put an attn instruction at 0x700
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921.bin tests: Put an attn instruction at 0x700
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922.bin tests: Put an attn instruction at 0x700
922.out Dump CTR, LR and CR on sim termination, and update our tests
923.bin tests: Put an attn instruction at 0x700
923.out Dump CTR, LR and CR on sim termination, and update our tests
924.bin tests: Put an attn instruction at 0x700
924.out Dump CTR, LR and CR on sim termination, and update our tests
925.bin tests: Put an attn instruction at 0x700
925.out Dump CTR, LR and CR on sim termination, and update our tests
926.bin tests: Put an attn instruction at 0x700
926.out Dump CTR, LR and CR on sim termination, and update our tests
927.bin tests: Put an attn instruction at 0x700
927.out Dump CTR, LR and CR on sim termination, and update our tests
928.bin tests: Put an attn instruction at 0x700
928.out Dump CTR, LR and CR on sim termination, and update our tests
929.bin tests: Put an attn instruction at 0x700
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930.bin tests: Put an attn instruction at 0x700
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931.bin tests: Put an attn instruction at 0x700
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932.bin tests: Put an attn instruction at 0x700
932.out Dump CTR, LR and CR on sim termination, and update our tests
933.bin tests: Put an attn instruction at 0x700
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934.bin tests: Put an attn instruction at 0x700
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935.bin tests: Put an attn instruction at 0x700
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936.bin tests: Put an attn instruction at 0x700
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937.bin tests: Put an attn instruction at 0x700
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938.bin tests: Put an attn instruction at 0x700
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939.bin tests: Put an attn instruction at 0x700
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940.bin tests: Put an attn instruction at 0x700
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941.bin tests: Put an attn instruction at 0x700
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942.bin tests: Put an attn instruction at 0x700
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943.bin tests: Put an attn instruction at 0x700
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944.bin tests: Put an attn instruction at 0x700
944.out Dump CTR, LR and CR on sim termination, and update our tests
945.bin tests: Put an attn instruction at 0x700
945.out Dump CTR, LR and CR on sim termination, and update our tests
946.bin tests: Put an attn instruction at 0x700
946.out Dump CTR, LR and CR on sim termination, and update our tests
947.bin tests: Put an attn instruction at 0x700
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948.bin tests: Put an attn instruction at 0x700
948.out Dump CTR, LR and CR on sim termination, and update our tests
949.bin tests: Put an attn instruction at 0x700
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950.bin tests: Put an attn instruction at 0x700
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951.bin tests: Put an attn instruction at 0x700
951.out Dump CTR, LR and CR on sim termination, and update our tests
952.bin tests: Put an attn instruction at 0x700
952.out Dump CTR, LR and CR on sim termination, and update our tests
953.bin tests: Put an attn instruction at 0x700
953.out Dump CTR, LR and CR on sim termination, and update our tests
954.bin tests: Put an attn instruction at 0x700
954.out Dump CTR, LR and CR on sim termination, and update our tests
955.bin tests: Put an attn instruction at 0x700
955.out Dump CTR, LR and CR on sim termination, and update our tests
956.bin tests: Put an attn instruction at 0x700
956.out Dump CTR, LR and CR on sim termination, and update our tests
957.bin tests: Put an attn instruction at 0x700
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958.bin tests: Put an attn instruction at 0x700
958.out Dump CTR, LR and CR on sim termination, and update our tests
959.bin tests: Put an attn instruction at 0x700
959.out Dump CTR, LR and CR on sim termination, and update our tests
960.bin tests: Put an attn instruction at 0x700
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961.bin tests: Put an attn instruction at 0x700
961.out Dump CTR, LR and CR on sim termination, and update our tests
962.bin tests: Put an attn instruction at 0x700
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963.bin tests: Put an attn instruction at 0x700
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964.bin tests: Put an attn instruction at 0x700
964.out Dump CTR, LR and CR on sim termination, and update our tests
965.bin tests: Put an attn instruction at 0x700
965.out Dump CTR, LR and CR on sim termination, and update our tests
966.bin tests: Put an attn instruction at 0x700
966.out Dump CTR, LR and CR on sim termination, and update our tests
967.bin tests: Put an attn instruction at 0x700
967.out Dump CTR, LR and CR on sim termination, and update our tests
968.bin tests: Put an attn instruction at 0x700
968.out Dump CTR, LR and CR on sim termination, and update our tests
969.bin tests: Put an attn instruction at 0x700
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970.bin tests: Put an attn instruction at 0x700
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971.bin tests: Put an attn instruction at 0x700
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972.bin tests: Put an attn instruction at 0x700
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973.bin tests: Put an attn instruction at 0x700
973.out Dump CTR, LR and CR on sim termination, and update our tests
974.bin tests: Put an attn instruction at 0x700
974.out Dump CTR, LR and CR on sim termination, and update our tests
975.bin tests: Put an attn instruction at 0x700
975.out Dump CTR, LR and CR on sim termination, and update our tests
976.bin tests: Put an attn instruction at 0x700
976.out Dump CTR, LR and CR on sim termination, and update our tests
977.bin tests: Put an attn instruction at 0x700
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978.bin tests: Put an attn instruction at 0x700
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979.bin tests: Put an attn instruction at 0x700
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980.bin tests: Put an attn instruction at 0x700
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981.bin tests: Put an attn instruction at 0x700
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987.bin tests: Put an attn instruction at 0x700
987.out Dump CTR, LR and CR on sim termination, and update our tests
988.bin tests: Put an attn instruction at 0x700
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989.bin tests: Put an attn instruction at 0x700
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Makefile.test tests: Fix Makefile.test to not allow host includes
micropython.bin tests: Add updated micropython build with 16550 support
test_decrementer.bin console: Add support for the 16550 UART
test_decrementer.console_out Add test cases for new exceptions and supervisor state
test_fpu.bin FPU: Implement floating multiply-add instructions
test_fpu.console_out FPU: Implement floating multiply-add instructions
test_illegal.bin console: Add support for the 16550 UART
test_illegal.console_out Add test cases for new exceptions and supervisor state
test_misc.bin tests/misc: Add a test for correct CTR and LR updating by branches
test_misc.console_out tests/misc: Add a test for correct CTR and LR updating by branches
test_mmu.bin MMU: Implement a vestigial partition table
test_mmu.console_out tests/mmu: Add a test of PTE refetching on permission error
test_modes.bin MMU: Implement a vestigial partition table
test_modes.console_out tests: Add tests for lq/stq and lqarx/stqcx.
test_privileged.bin MMU: Implement a vestigial partition table
test_privileged.console_out tests: Add tests for the PVR
test_reservation.bin tests: Add tests for lq/stq and lqarx/stqcx.
test_reservation.console_out tests: Add tests for lq/stq and lqarx/stqcx.
test_sc.bin console: Add support for the 16550 UART
test_sc.console_out Add test cases for new exceptions and supervisor state
test_spr_read.bin MMU: Implement a vestigial partition table
test_spr_read.console_out MMU: Implement a vestigial partition table
test_trace.bin tests/trace: Test trace interrupt vs. FP unavailable interrupt
test_trace.console_out tests/trace: Test trace interrupt vs. FP unavailable interrupt
test_xics.bin console: Add support for the 16550 UART
test_xics.console_out xics: Add simple ICS
update_console_tests Add a test to read from all SPRs