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83d773090e
Fix verific script with new VHDL files
#18
Michael Neuling 2019-09-06 15:05:01 +1000
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a15eb4e28d
Anton Blanchard 2019-09-06 10:09:26 +1000
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147b259691
Use a better input signal in writeback
#17
Anton Blanchard 2019-09-06 09:46:55 +1000
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3f59396907
Anton Blanchard 2019-09-04 06:33:40 +1000
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5e140298a5
Rework decode2
#16
Anton Blanchard 2019-09-03 12:44:03 +1000
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d1fdc286c4
Anton Blanchard 2019-08-31 13:34:38 +1000
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4d5abfb430
Remove dynamic ranges from code
#13
Michael Neuling 2019-08-29 09:47:45 +1000
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7a85e3877d
Anton Blanchard 2019-08-30 09:06:48 +1000
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5379b805ec
Arty A7 reset pin is C2
#10
Anton Blanchard 2019-08-30 08:39:44 +1000
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3819768d2a
Anton Blanchard 2019-08-30 08:38:13 +1000
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5aba4e7346
Anton Blanchard 2019-08-30 08:26:35 +1000
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6c8d28a642
A few Travis CI fixes
#9
Anton Blanchard 2019-08-30 08:12:54 +1000
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4ebd6fc1f7
Added support for building for Arty A7 boards
#7
riktw 2019-08-27 22:20:02 +0200
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f98370f9e6
Anton Blanchard 2019-08-29 07:46:51 +1000
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2ee269abdb
Add an initial travis.yml
#5
Anton Blanchard 2019-08-27 10:40:43 +1000
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0fd18c2455
Add srd and srw
Anton Blanchard 2019-08-28 14:50:11 +1000
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73daacbcd4
Add sim only divw
Anton Blanchard 2019-08-28 14:07:29 +1000
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95b9f19882
Fix ghdl build error with pp_soc_memory
Anton Blanchard 2019-08-27 22:12:33 +1000
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1fa0b332ca
micropython only requires 512kB of BRAM
Anton Blanchard 2019-08-27 12:02:00 +1000
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1aadee281d
Anton Blanchard 2019-08-27 11:50:25 +1000
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96787091a6
Add -Wall to CFLAGS
Anton Blanchard 2019-08-27 11:44:34 +1000
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d618171d13
Add pretty gif demo of MicroPython on Microwatt to README.md
#6
Michael Neuling 2019-08-27 11:19:15 +1000
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7277c6b5ab
Add missing argument to fprintf warning
Anton Blanchard 2019-08-26 23:11:51 +1000
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77f1588a7f
Add some initial FPGA synthesis instructions
Anton Blanchard 2019-08-26 22:32:15 +1000
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0a0ad9b384
Rebuild hello world assuming a 50MHz clock
Anton Blanchard 2019-08-26 12:33:15 +1000
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c036363d8f
Anton Blanchard 2019-08-26 22:02:17 +1000
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12327034d6
Add and use plle2 primitive for nexys boards
#3
Olof Kindgren 2019-08-24 11:25:21 +0200
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5b2984a15d
Anton Blanchard 2019-08-26 11:33:38 +1000
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2d7994dc12
don't cross compile when on Power
#4
Dan Horák 2019-08-24 14:02:35 +0200
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8bc3e8ea0a
Add a simple hello_world example that also echos input
Anton Blanchard 2019-08-24 08:59:17 +1000
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01e6b8f583
Anton Blanchard 2019-08-24 05:25:48 +1000
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b9bf19f912
Added synthesis target
#2
Olof Kindgren 2019-08-23 14:20:20 +0200
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250d09ed2d
Add Nexys Video support
Olof Kindgren 2019-08-23 14:09:06 +0200
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5e56b14125
Add FuseSoC core description file with Nexys A7 support
Olof Kindgren 2019-08-23 13:32:05 +0200
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abca85b034
Add constraint file for Nexys A7
Olof Kindgren 2019-08-23 13:19:11 +0200
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e8ad9bed10
Expose ram init file and memory size through toplevel
Olof Kindgren 2019-08-23 13:18:39 +0200
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b5bccc4c13
Add dummy clock generator
Olof Kindgren 2019-08-23 13:17:35 +0200
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37fe8b954c
Add a few more FPGA related files
Anton Blanchard 2019-08-23 16:23:53 +1000
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5a29cb4699
Initial import of microwatt
Anton Blanchard 2019-08-22 16:46:13 +1000