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caravel-mpw7-20221125
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trace-test
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litedram-update
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fix-sdcard
fpu-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
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boxarty-20211011
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remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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4 Commits (efb387b0d23e28e05d8fd19b3f5d8009f8fbd78b)

Author SHA1 Message Date
Benjamin Herrenschmidt 079af6443e litedram: Update generator to work with latest LiteX 
Some changes in LiteX broke us. Adapt the build system and
increase the init RAM size to 24KB.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 63f10450a6 litedram: Fix DRAM init mem using too many address bits 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt bf1b98b958 litedram: Add support for booting without BRAM 
This adds an option to disable the main BRAM and instead copy a
payload stashed along with the init code in the secondary BRAM
into DRAM and boot from there

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 12f36b4a35 litedram: Split the init memory from the main wrapper 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago