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caravel-mpw7-20221125
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litedram-update
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3 Commits (e0bf743d7ae5a40480e1b5df1831925383e9fba5)

Author SHA1 Message Date
Anton Blanchard 83fe8b629c litesdcard: Fix and regenerate Verilog 
Fix the litex generate script to pass frequencies in Hz. Regenerate
the litesdcard Verilog for both Xilinx and Lattice. This fixes
litesdcard on my Nexys Video.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Matt Johnston 42959184dd litesdcard: add lattice, regenerate 
Modifies litescard generate script to take a clock speed.

Regenerated verilog with latest litesdcard
e52c731 ("Bump year.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 3 years ago
Anton Blanchard 9caaa3fc46 litesdcard: Use vendor not board type 
litesdcard provides a macro per vendor (eg xilinx, lattice) and not per
board, so modify the fusesoc generator to take a vendor. This will make
it easier to add litesdcard to more boards.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago