Commit Graph

810 Commits (d839037f0b5ede23a2a661d3f46b421605e45fe5)
 

Author SHA1 Message Date
Anton Blanchard 4e977bf8a9
Merge pull request #220 from mikey/ghdl-makefile
Use $(GHDL) rather than ghdl in Makefile
4 years ago
Anton Blanchard 65fc34cf6e
Merge pull request #209 from mikey/yosys
Make yosys/nextpnr work and add to CI
4 years ago
Jordan Niethe 17fc77cef2 core: Implement PVR register
Microwatt has been allocated a PVR version of 0x0063. Implement a PVR
with this value.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
4 years ago
Michael Neuling 1697f8a08f Use $(GHDL) rather than ghdl in Makefile
Suggestion from @eine in PR #219.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 8bfc6a21b9 Add yosys/nextpnr ecp5 and verilog build to CI
This works now, so let's make sure it continues to.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 10a1a86ba0 Add FPGA_TARGET=ECP5-EVN make option for synthesis build
This allows these targets
  FPGA_TARGET=ORANGE-CRAB make microwatt.bit
  FPGA_TARGET=ECP5-EVN make microwatt.bit
Default is ORANGE-CRAB as before

ECP5-EVN is tested on real hardware. The console only works at 38400 so
needs this in console.c and a recompile of hello_world to work:

  -#define UART_FREQ 115200
  +#define UART_FREQ 38400

With this 'FPGA_TARGET=ECP5-EVN make prog' works on the ECP5 dev board.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling ef0dcf3bc6 Add SYNTH_ECP5_FLAGS option for building
This is useful to specify "-noflatten" which helps CI stay under 8GB
limit.

Normally the AUTONAME stage of yosys will take around 10GB if
operating on the whole design. With -noflatten, AUTONAME occurs only
per VHDL entity, so only consumes around 3GB of memory. This gets us
under the limitations on github actions.

More discussion here:
  https://github.com/antonblanchard/microwatt/pull/209#issuecomment-652186078

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 45fd2354f2 Add ram file to synthesis build dependencies
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 7347786b08 Add uart16550 files to yosys/nextpnr build
These are verilog so need passed to yosys differently than the VHDL
files.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling aae45583d7 Add uart16550 files from fusesoc
These are needed for synthesis that doesn't use fusesoc natively.

These were pulled in via 'fusesoc fetch ::uart16550:1.5.5-r1'

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 3f6d48f2fc Build to tmp file so nextpnr errors don't confuse make
nextpnr will leave an output file around even when it errors out, so
build to a tmp file and move it when we succeed so we don't confuse
make.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 3e0ac8c94c Fix building with yosys/nextpnr
Add --no-formal so that asserts are removed by yosys as nextpnr
doesn't like them.

This was suggested by @tgingold here:
  https://github.com/YosysHQ/yosys/issues/2068#issuecomment-644545863

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 3460afb557 Add yosys builds files to gitignore
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling b1c260599f Send line feed if we get a carriage return in hello world.
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling ce0205b262
Merge pull request #216 from paulusmack/cfar
Timing and speed improvements, implement CFAR register
4 years ago
Paul Mackerras 419c9a68e8
Merge pull request #206 from Jbalkind/icachecleanup
Icache constants cleanup
4 years ago
Paul Mackerras 74062195ca execute1: Do forwarding of the CR result to the next instruction
This adds a path to allow the CR result of one instruction to be
forwarded to the next instruction, so that sequences such as
cmp; bc can avoid having a 1-cycle bubble.

Forwarding is not available for dot-form (Rc=1) instructions,
since the CR result for them is calculated in writeback.  The
decode.output_cr field is used to identify those instructions
that compute the CR result in execute1.

For some reason, the multiply instructions incorrectly had
output_cr = 1 in the decode tables.  This fixes that.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 0f0573903b execute1: Add latch to redirect path
This latches the redirect signal inside execute1, so that it is sent
a cycle later to fetch1 (and to decode/icache as flush).  This breaks
a long combinatorial chain from the branch and interrupt detection
in execute1 through the redirect/flush signals all the way back to
fetch1, icache and decode.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 9b40b5a77b logical: Only do output inversion for OP_AND, OP_OR and OP_XOR
It's not needed for the other ops (popcnt, parity, etc.) and the
logical unit shows up as a critical path from time to time.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras c2da82764f core: Implement CFAR register
This implements the CFAR SPR as a slow SPR stored in 'ctrl'.  Taken
branches and rfid update it to the address of the branch or rfid
instruction.

To simplify the logic, this makes rfid use the branch logic to
generate its redirect (requiring SRR0 to come in to execute1 on
the B input and SRR1 on the A input), and the masking of the bottom
2 bits of NIA is moved to fetch1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Michael Neuling 57604c1a6e
Merge pull request #213 from ozbenh/uart16550
Add support for standard 16550 style UART
4 years ago
Michael Neuling 9bbef035a6
Merge pull request #212 from ozbenh/liteeth
liteeth: Hook up LiteX LiteEth ethernet controller
4 years ago
Michael Neuling cc27e239f4
Merge pull request #214 from shingarov/fix-ld-target
Fix ld error in elf maketarget
4 years ago
Boris Shingarov 49f1389a21 Fix ld error in elf maketarget
The sdram_init ELF fails to link:

powerpc64le-linux-gnu-ld -static -nostdlib -T sdram_init.lds \
    --gc-sections -o sdram_init.elf head.o main.o sdram.o console.o \
    libc.o sdram_init.lds
powerpc64le-linux-gnu-ld: error: linker script file 'sdram_init.lds'
    appears multiple times
make: *** [Makefile:70: sdram_init.elf] Error 1

This is because sdram_init.lds is one of the prerequisites, and thus is
contained in $^.  However, it is also explicitly specified as part of
LDFLAGS, as the argument to -T.

Signed-off-by: Boris Shingarov <shingarov@labware.com>
4 years ago
Benjamin Herrenschmidt 434962bc34 tests: Add updated micropython build with 16550 support
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt fc4e13ae67 sim_console: Fix polling to check for POLLIN
Under some circumstances we get POLLHUP which we incorrectly
treat as having a character in the buffer.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt fb5c16d05e uart: Make 16550 the default
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt b230677e93 syscon: Add flag to indicate the timebase frequency
This adds a flag (currently not set) to indicate that the core is using
the architected timebase frequency of 512Mhz. When not set, the core is
using the proc frequency for the timebase.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt d654667304 console: Add support for the 16550 UART
And rebuild various binaries

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt cc10f6b289 uart: Add a simulation model for the 16550 compatible UART
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 4eae29801b uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt e3941109af console: Cleanup console API
Use a more generic console_init() instead of potato_uart_init(),
and do the same for interrupt control. There should be no
change in behaviour.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 7575b1e0c2 uart: Import and hook up opencore 16550 compatible UART
This imports via fusesoc a 16550 compatible (ie "standard") UART,
and wires it up optionally in the SoC instead of the potato one.

This also adds support for a second UART (which is always a
16550) to Arty, wired to JC "bottom" port.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 76e2c7d81c ex1: Add SPR_TBU support
It's used by the boot wrapper in Linux and possibly some userspace
programs.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller
Currently only generated for Arty.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Michael Neuling 7566f04fe3
Merge pull request #211 from shenki/spi-constraint
spi: Fix dat_i_l constraints
4 years ago
Joel Stanley 60e5f7b958 spi: Fix dat_i_l constraints
No cells matched 'get_cells -hierarchical -filter {NAME =~*/spi_rxtx/dat_i_l*}'. [build/microwatt_0/src/microwatt_0/fpga/arty_a7.xdc:42]

The signal is in it's own process so the net name ends up being
spi_rxtx/input_delay_1.dat_i_l_reg.

After this change the log shows:

Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file  fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file  fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file  fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file  fpga/arty_a7.xdc, line 42).

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years ago
Michael Neuling 695e081c35
Merge pull request #210 from ozbenh/xics
xics: Cleanups and add a simple ICS for use by Linux
4 years ago
Benjamin Herrenschmidt bb54af59de xics: Add support for reduced priority field size
This makes the ICS support less than the 8 architected bits
and sets the soc to use 3 bits by default.

All the supported bits set translates to "masked" (and will read
back at 0xff), any small value is used as-is.

Linux doesn't use priorities above 5, so this is a way to save
silicon. The number of supported priority bits is exposed to the
OS via the config register.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 5c2fc47e2c xics: Add simple ICS
Move the external interrupt generation to a separate module
"ICS" (source controller) which a register per source containing
currently only the priority control.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 8080168327 xics/icp: MFRR starts at 0xff not 0x00
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 0b82024b01 tests/xics: Ensure no compiler optimisations in delay()
In case it would be tempted to "read ahead" the delay function

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 0fa14f6dec xics: ICP should be big endian !
That's how Linux expects it. This also simplifies the
register access implementation since the bit fields now
align properly regardless of the access size.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 311b653d80 tests: Fix Makefile.test to not allow host includes
xics was including the host limits.h for example

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Michael Neuling b90a0a2139
Merge pull request #208 from paulusmack/faster
Make the core go faster

Several major improvements in here:
- Simple branch predictor
- Reduced latency for mispredicted branches and interrupts by removing fetch2 stage
- Cache improvements
  o Request critical dword first on refill
  o Handle hits while refilling, including on line being refilled
  o Sizes doubled for both D and I
- Loadstore improvements: can now do one load or store every two cycles in most cases
- Optimized 2-cycle multiplier for Xilinx 7-series parts using DSP slices
- Timing improvements, including:
  o Stash buffer in decode1
  o Reduced width of execute1 result mux
  o Improved SPR decode in decode1
  o Some non-critical operation take a cycle longer so we can break some long combinatorial chains
- Core logging: logs 256 bits of info every cycle into a ring buffer, to help with debugging and performance analysis

This increases the LUT usage for the "synth" + A35 target from 9182 to 10297 = 12%.
4 years ago
Paul Mackerras 1fedc7a86a
Merge pull request #207 from ozbenh/misc
Random cleanups of the SoC interfaces
4 years ago
Paul Mackerras 64efd494e5 fpga: Add a xilinx_specific fileset to microwatt.core
At present this just has the Xilinx-specific multiplier code, but
might in future have other things.

This also adds the xilinx_specific fileset to the synth target.
Without that it was failing because there was no multiplier.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 78de4fef72 Make LOG_LENGTH configurable per FPGA variant
This plumbs the LOG_LENGTH parameter (which controls how many entries
the core log RAM has) up to the top level so that it can be set on
the fusesoc command line and have different default values on
different FPGAs.

It now defaults to 512 entries generally and on the Artix-7 35 parts,
and 2048 on the larger Artix-7 FPGAs.  It can be set to 0 if desired.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras ec2fa61792 execute1: Reduce width of the result mux to help timing
This reduces the number of different things that are assigned to
the result variable.

- The computations for the popcnt, prty, cmpb and exts instruction
  families are moved into the logical unit.
- The result of mfspr from the slow SPRs is computed in 'spr_val'
  before being assigned to 'result'.
- Writes to LR as a result of a blr or bclr instruction are done
  through the exc_write path to writeback.

This eases timing considerably.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 6687aae4d6 core: Implement a simple branch predictor
This implements a simple branch predictor in the decode1 stage.  If it
sees that the instruction is b or bc and the branch is predicted to be
taken, it sends a flush and redirect upstream (to icache and fetch1)
to redirect fetching to the branch target.  The prediction is sent
downstream with the branch instruction, and execute1 now only sends
a flush/redirect upstream if the prediction was wrong.  Unconditional
branches are always predicted to be taken, and conditional branches
are predicted to be taken if and only if the offset is negative.
Branches that take the branch address from a register (bclr, bcctr)
are predicted not taken, as we don't have any way to predict the
branch address.

Since we can now have a mflr being executed immediately after a bl
or bcl, we now track the update to LR in the hazard tracker, using
the second write register field that is used to track RA updates for
update-form loads and stores.

For those branches that update LR but don't write any other result
(i.e. that don't decrementer CTR), we now write back LR in the same
cycle as the instruction rather than taking a second cycle for the
LR writeback.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago