microwatt

Commit Graph

Author	SHA1	Message	Date
Paul Mackerras	c1f23e7417	litesdcard: Regenerate verilog code with buffer direction controls This regenerates the verilog code from upstream litex plus a patch to generate outputs from the litesdcard module for controlling bidirectional buffers between the FPGA and SD card. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	2 years ago
Paul Mackerras	264e609fd4	litesdcard: Name targets by vendor.frequency, not just vendor In future we will want to support targets using the same vendor but running at different clock frequencies. Since the clock frequency is a parameter to the gateware generation process, we now name the target directories as "vendor.frequency", i.e., "xilinx.100e6" and "lattice.48e6" rather than "xilinx" and "lattice". Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	2 years ago

Author

SHA1

Message

Date

Paul Mackerras

c1f23e7417

litesdcard: Regenerate verilog code with buffer direction controls

This regenerates the verilog code from upstream litex plus a patch to
generate outputs from the litesdcard module for controlling
bidirectional buffers between the FPGA and SD card.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

Paul Mackerras

264e609fd4

litesdcard: Name targets by vendor.frequency, not just vendor

In future we will want to support targets using the same vendor but
running at different clock frequencies.  Since the clock frequency is
a parameter to the gateware generation process, we now name the target
directories as "vendor.frequency", i.e., "xilinx.100e6" and
"lattice.48e6" rather than "xilinx" and "lattice".

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

2 Commits (d531e8aa1077f81f0b48d8112b3c5d9af684d453)