cores
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microwatt
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caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
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core_debug-init
icache-unused-sig
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fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
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nia-debug
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Commit Graph

5 Commits (d0ced7441f695164ac388a26c114f49be55a122e)

Author SHA1 Message Date
Anton Blanchard 606359cce3 Add simplebus 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 49b332e17f Hook up JTAG to ASIC top level 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard c2577b5446 Add ASIC target 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 5249d633cf Move register stage from after RAM to before RAM 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 8ecb30da05 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago