Commit Graph

835 Commits (c6dfc19d890bcf79f59cb8e68e23a50214ef1b60)
 

Author SHA1 Message Date
Benjamin Herrenschmidt 3687486d36 Update hello_world for 100Mhz clock
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 0f97b320f6 Change default frequency to 100Mhz
LiteDRAM at the moment pretty much enforces 100Mhz, and our software
isn't quite yet adaptable, so switch out default to 100Mhz accross
the board. Recent timing improvements should make it a non-issue.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt f124dc4a40 xics: Add missing fusesoc core file
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Joel Stanley 8857bd1f58 Add openocd SPI flashing proxies for Arty
These are downloaded from https://github.com/quartiq/bscan_spi_bitstreams/

Signed-off-by: Joel Stanley <joel@jms.id.au>
5 years ago
Anton Blanchard 1ba29a407a
Merge pull request #166 from paulusmack/master
MSR fixes, implement privilege checking, implement dcbz
5 years ago
Paul Mackerras 102fbcfe9a execute1: Fix interrupt delivery during slow instructions
During slow instructions such as multiply or divide, if a decrementer
(or other asynchronous) interrupt becomes pending, it disrupts the
logic that keeps stall asserted until the end of the slow
instruction, and the interrupt logic starts trying to deliver the
interrupt before the slow instruction has finished.

To fix that, make the interrupt logic wait until it sees e_in.valid
set before setting exception to 1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras fe789190e4 wishbone_debug_master: Fix address auto-increment for memory writes
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 102b304db7 Merge remote-tracking branch 'remotes/origin/master' 5 years ago
Paul Mackerras 4db1676ef8 dcache: Don't assert on dcbz cache hit
We can hit the assert for req_op = OP_STORE_HIT and reloading in the
case of dcbz, since it looks like a store.  Therefore we need to
exclude that case from the assert.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Anton Blanchard 4160f2138d
Merge pull request #165 from mikey/xics
Implement XICS compliant interrupt controller
5 years ago
Anton Blanchard 098c3fbb2b
Merge pull request #167 from tomtor/patch-1
Fix Rust README.md
5 years ago
Tom Vijlbrief c818853a1c Update README.md
Fix formatting of Rust README

Signed-off-by: Tom Vijlbrief <tvijlbrief@gmail.com>
5 years ago
Paul Mackerras cf4dfeca36 Change the default cross compiler prefix to powerpc64le-linux-gnu-
That is what is used by the packaged cross-compilers on (at least)
Fedora and Ubuntu.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras a05ee9fc7f Makefile: fix typo
Fix a typo which meant that the console tests weren't getting
executed by 'make check'.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 10f4be4309 tests: Add a test for privileged instruction interrupts
This adds a test that tries to execute various privileged instructions
with MSR[PR] = 1.  This also incidentally tests some of the MSR bit
manipulations.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 041d6bef60 dcache: Implement the dcbz instruction
This adds logic to dcache and loadstore1 to implement dcbz.  For now
it zeroes a single cache line (by default 64 bytes), not 128 bytes
like IBM Power processors do.

The dcbz operation is performed much like a load miss, except that
we are writing zeroes to memory instead of reading.  As each ack
comes back, we write zeroes to the BRAM instead of data from memory.
In this way we zero the line in memory and also zero the line of
cache memory, establishing the line in the cache if it wasn't already
resident.  If it was already resident then we overwrite the existing
line in the cache.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 167e37d667 Plumb insn_type through to loadstore1
In preparation for adding a TLB to the dcache, this plumbs the
insn_type from execute1 through to loadstore1, so that we can have
other operations besides loads and stores (e.g. tlbie) going to
loadstore1 and thence to the dcache.  This also plumbs the unit field
of the decode ROM from decode2 through to execute1 to simplify the
logic around which ops need to go to loadstore1.

The load and store data formatting are now not conditional on the
op being OP_LOAD or OP_STORE.  This eliminates the inferred latches
clocked by each of the bits of r.op that we were getting previously.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 74db071067 execute1: Generate privileged instruction interrupts when MSR[PR] = 1
This adds logic to execute1 to check, when MSR[PR] = 1, whether each
instruction arriving to be executed is a privileged instruction.
If it is, a privileged-instruction type program interrupt is generated.
For the mtspr and mfspr instructions, we need to look at bit 20 of the
instruction (bit 4 of the SPR number) to determine if the SPR is
privileged.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras b55c9cc298 execute1: Improve architecture compliance of MSR and related instructions
This makes our treatment of the MSR conform better with the ISA.

- On reset, initialize the MSR to have the SF and LE bits set and
  all the others reset.  For good measure initialize r properly too.

- Fix the bit numbering in msr_copy (the code was using big-endian
  bit numbers, not little-endian).

- Use constants like MSR_EE to index MSR bits instead of expressions
  like '63 - 48', for readability.

- Set MSR[SF, LE] and clear MSR[PR, IR, DR, RI] on interrupts.

- Copy the relevant fields for rfid instead of using msr_copy, because
  the partial function fields of the MSR should be left unchanged,
  not zeroed.  Our implementation of rfid is like the architecture
  description of hrfid, because we don't implement hypervisor mode.

- Return the whole MSR for mfmsr.

- Implement the L field for mtmsrd (L=1 copies just EE and RI).

- For mtmsrd with L=0, leave out the HV, ME and LE bits as per the arch.

- For mtmsrd and rfid, if PR ends up set, then also set EE, IR and DR
  as per the arch.

- A few other minor tidyups (no semantic change).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Anton Blanchard f21f9dd5a0
Merge pull request #164 from mikey/tags
Add VHDL TAGS
5 years ago
Anton Blanchard b6bd1ba33d
Merge pull request #163 from paulusmack/excpath
Fix the bug causing the assert that Mikey hit
5 years ago
Michael Neuling 0076f8bf1d XICS test case
Checks interrupt masking and priorities.

Adds to `make test_xics` which is run in `make check` also.

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Michael Neuling b4f20c20b9 XICS interrupt controller
New unified ICP and ICS XICS compliant interrupt controller.
Configurable number of hardware sources.

Fixed hardware source number based on hardware line taken. All
hardware interrupts are a fixed priority. Level interrupts supported
only.

Hardwired to 0xc0004000 in SOC (UART is kept at 0xc0002000).

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Michael Neuling e5a30a1358 Wire up sim uart TX interrupt
TX is always ready, so just always sent interrupt when enabled.

No RX interrupt.

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Michael Neuling fc5f7506f8 Add calls to dis/enable potato uart IRQ
Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Michael Neuling ff162e42eb Add VHDL TAGS
Adds `make TAGS`

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Paul Mackerras dc6b1df653 execute1: Don't execute ld/st instruction when taking interrupt
This fixes a bug in the logic where we would still send a load
or store instruction to loadstore1 even though we have decided
to take an asynchronous interrupt.

Reported-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Anton Blanchard 2b11c81b18
Merge pull request #162 from antonblanchard/bin2hex-removal
rust_lib_demo: Remove bin2hex.py
5 years ago
Anton Blanchard 4c2bd76634
Merge pull request #161 from antonblanchard/hello-world-Makefile
hello_world: Use Makefile automatic variables
5 years ago
Anton Blanchard 05f4f68c54 rust_lib_demo: Remove bin2hex.py
We are using scripts/bin2hex.py, so we can get rid of this copy.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard afbb99cfd4
Merge pull request #160 from antonblanchard/tomtor-rust-2
Rebase Tom's rust demo patches
5 years ago
Anton Blanchard 06b28be577 hello_world: Use Makefile automatic variables
Fix a few whitespace issues while here.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 90ed7adf58 rust_lib_demo: Use common console code
Use a symlink to share the console code in hello_world. Not ideal,
but we can improve on it later.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard c37a4c16db rust_lib_demo: Update package dependencies to fix a build error
I'm hitting a build error:

    error[E0050]: method `alloc` has 2 parameters but the declaration in trait `core::alloc::AllocRef::alloc` has 3

Updating the version of linked_list_allocator fixes it. I updated
heapless to while I was at it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Tom Vijlbrief ae55f5efbd Add Rust demo
Signed-off-by: Tom Vijlbrief <tvijlbrief@gmail.com>
5 years ago
Anton Blanchard d511e088d2
Merge pull request #159 from shenki/fusesoc-ram-16k
FuseSoC needs 16kB of RAM
5 years ago
Joel Stanley 6a3d2d95df Set default RAM to be 16K in microwatt.core
This allows it to run hello world out of the box.

Signed-off-by: Joel Stanley <joel@jms.id.au>
5 years ago
Joel Stanley 04b784011a README: hello world needs 16KB of RAM
STACK_TOP is at 0x2000 (8K) so we need something larger as a minimum.

Signed-off-by: Joel Stanley <joel@jms.id.au>
5 years ago
Anton Blanchard 97e3d47a13
Merge pull request #158 from paulusmack/excpath
Fix exception stuff so we make timing again
5 years ago
Anton Blanchard e8a55f900f
Merge pull request #157 from paulusmack/master
Start using cache-inhibited loads and stores to access the UART
5 years ago
Paul Mackerras 56577827d4 Decode attn in the major opcode decode table
This decodes attn using entry 0 of the major_decode_rom_array table
instead of a special case in the decode1_1 process.  This means that
only the major opcode (the top 6 bits) is checked at decode time.
To make sure the instruction is attn not some random illegal pattern,
we now check bits 1-10 of the instruction at execute time and
generate an illegal instruction interrupt if those bits are not
0100000000.

This reduces LUT consumption by 42 LUTs on the Arty A7-100.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 6f7ef8b1b9 Decode sc in the major opcode decode table
This decodes sc using entry 17 of the major_decode_rom_array table
instead of a special case in the decode1_1 process.  This means that
only the major opcode (the top 6 bits) is checked at decode time.
To make sure that the instruction is sc not scv, we now check bit
1 of the instruction at execute time and generate an illegal
instruction interrupt if it is 0 (indicating scv).  The level field
of the sc instruction is now ignored.

This reduces LUT consumption by 31 LUTs on the Arty A7-100.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 278ac5e0eb Remove sim_config instruction
It's not used any more, and it's not in the ISA.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras f5f17c24fd execute1: Implement trap instructions properly
This implements the trap instructions (tw, twi, td, tdi) using
much of the same code as is used for the cmp/cmpl instructions.
A 5-bit comparison value is generated, and for cmp/cmpl, the
appropriate 3 bits are used to update the destination CR, and for
trap instructions, the comparison value is ANDed with the TO
field, and an exception is generated if any bit of the result
is 1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 381149b2cc Consolidate trap variants under a single OP_TRAP
This replaces OP_TD, OP_TDI, OP_TW and OP_TWI with a single OP_TRAP,
distinguishing the cases by the input_reg_b and is_32bit fields of
the decode ROM.  This adds the twi and td cases to the decode tables.

For now we make all of the trap instructions unconditionally generate
a trap-type program interrupt if the TO field of the instruction is
all ones, and do nothing otherwise.

This reduces the number of values in insn_type_t from 65 to 62,
meaning that an insn_type_t can now be encoded in 6 bits rather
than 7.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras d77033aa92 execute1: Simplify the interrupt logic a little
This makes some simplifications to the interrupt logic which will
help with later commits.

- When irq_valid is set, don't set exception to 1 until we have a
  valid instruction.  That means we can remove the if e_in.valid = '1'
  test from the exception = '1' block.

- Don't assert stall_out on the first cycle of delivering an
  interrupt.  If we do get another instruction in the next cycle,
  nothing will happen because we have ctrl.irq_state set and we
  will just continue writing the interrupt registers.

- Make sure we deliver as many completions as we got instructions,
  otherwise the outstanding instruction count in control.vhdl gets
  out of sync.

- In writeback, make sure all of the other write enables are ignored
  when e_in.exc_write_enable is set.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras fe077a116a Rename OP_MCRF to OP_CROP and trim insn_type_t
OP_MCRF covers the CR logical ops as well as mcrf since commit
c05441bf47 ("Implement CRNOR and friends"), so this renames
OP_MCRF to OP_CROP.  The OP_* values for the individual CR logical
ops (OP_CRAND, etc.) are not used, so remove them from insn_type_t.

No functional change.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 0a95e4bfdd tests: Put an attn instruction at 0x700
This puts an attn instruction at offset 0x700 in each of the tests
so that the test will terminate if a program interrupt is taken.
This means that we can implement the tw instruction to cause a
program interrupt.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras fb8f3da128 Give exceptions a separate path to writeback
This adds separate fields in Execute1ToWritebackType for use in
writing SRR0/1 (and in future other SPRs) on an interrupt.  With
this, we make timing once again on the Arty A7-100 -- previously
we were missing by 0.2ns, presumably due to the result mux being
wider than before.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras e990e9c839 tests: Update executables
As suggested by Michael Neuling.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago