Commit Graph

3 Commits (c5f5f507385dd9d2dad62908c79d911d237a4eda)

Author SHA1 Message Date
Benjamin Herrenschmidt 12e8b0952d litedram: Improve sdram init boot messages
Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Benjamin Herrenschmidt 025cf5efe8 syscon: Add syscon registers
These provides some info about the SoC (though it's still somewhat
incomplete and needs more work, see comments).

There's also a control register for selecting DRAM vs. BRAM at 0
(and for soft-resetting the SoC but that isn't wired up yet).

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Benjamin Herrenschmidt 982cf166dd litedram: Add basic support for LiteX LiteDRAM
This comes in two parts:

 - A generator script which uses LiteX to generate litedram cores
along with their init files for various boards (currently Arty and
Nexys-video). This comes with configs for arty and nexys_video.

 - A fusesoc "generator" which uses pre-generated litedram cores

The generation process is manual on purpose. This include pre-generated
cores for the two above boards.

This is done so that one doesn't have to install LiteX to build
microwatt. In addition, the generator script or wrapper vhdl tend to
break when LiteX changes significantly which happens.

This is still rather standalone and hasn't been plumbed into the SoC
or the FPGA toplevel files yet.

At this point LiteDRAM self-initializes using a built-in VexRiscv
"Minimum" core obtained from LiteX and included in this commit. There
is some plumbing to generate and cores that are initialized by Microwatt
directly but this isn't working yet and so isn't enabled yet.

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago