Commit Graph

1 Commits (c083b9507dafee86c5c0c14d6e1ef8c56a2b8a3f)

Author SHA1 Message Date
Anton Blanchard 3e8a6a8fc2 Add yosys/verilator support
Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago