Commit Graph

5 Commits (bb5f3563867d66ce2848c5853a6d2b4177d98e69)

Author SHA1 Message Date
Anton Blanchard 7994b98404 Fix some whitespace issues
Signed-off-by: Anton Blanchard <>
3 years ago
Anton Blanchard 5eb351b4be Reset JTAG/DMI
request is never initialized and we leak X state control signals to other
parts of the core (eg dmi_wr). Add a reset.

Signed-off-by: Anton Blanchard <>
4 years ago
Benjamin Herrenschmidt 9b458a9aa6
dmi: Add ASYNC_REG attribute on synchronizers (#200)
This tells Vivado to keep them close among other things

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Benjamin Herrenschmidt 5f28109957 Don't reset JTAG request register asynchronously
There's no point and it causes Vivado to spew a pile of warnings

Signed-off-by: Benjamin Herrenschmidt <>
5 years ago
Benjamin Herrenschmidt ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
This adds a simple bus that can be mastered from an external
system via JTAG, which will be used to hookup various debug

It's loosely based on the RiscV model (hence the DMI name).

The module currently only supports hooking up to a Xilinx BSCANE2
but it shouldn't be too hard to adapt it to support different TAPs
if necessary.

The JTAG protocol proper is not exactly the RiscV one at this point,
though I might still change it.

This comes with some sim variants of Xilinx BSCANE2 and BUFG and a
test bench.

Signed-off-by: Benjamin Herrenschmidt <>
5 years ago