Commit Graph

2 Commits (bb5f3563867d66ce2848c5853a6d2b4177d98e69)

Author SHA1 Message Date
Anton Blanchard 8102e7863b Fix build issue in dmi_dtm_dummy.vhdl
Signed-off-by: Anton Blanchard <>
5 years ago
Benjamin Herrenschmidt ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
This adds a simple bus that can be mastered from an external
system via JTAG, which will be used to hookup various debug

It's loosely based on the RiscV model (hence the DMI name).

The module currently only supports hooking up to a Xilinx BSCANE2
but it shouldn't be too hard to adapt it to support different TAPs
if necessary.

The JTAG protocol proper is not exactly the RiscV one at this point,
though I might still change it.

This comes with some sim variants of Xilinx BSCANE2 and BUFG and a
test bench.

Signed-off-by: Benjamin Herrenschmidt <>
5 years ago