This looks for cases where the next 8 bits of the quotient are obviously
going to be zero, because the top 72 bits of the 128-bit dividend
register are all zero. In those cases we shift 8 zero bits into the
quotient and increase count by 8. We only do this if count < 56.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

This adds a divider unit, connected to the core in much the same way
that the multiplier unit is connected. The division algorithm is
very simple-minded, taking 64 clock cycles for any division (even
32-bit division instructions).
The decoding is simplified by making use of regularities in the
instruction encoding for div* and mod* instructions. Instead of
having PPC_* encodings from the first-stage decoder for each of the
different div* and mod* instructions, we now just have PPC_DIV and
PPC_MOD, and the inputs to the divider that indicate what sort of
division operation to do are derived from instruction word bits.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>