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4 Commits (a22afbdb5b87a841899f56c76a59e39c6a84f0b2)

Author SHA1 Message Date
Michael Neuling 4d5abfb430 Remove dynamic ranges from code 
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.

Also add basic script to run verific and generate verilog.

1. https://www.verific.com/

Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard 0fd18c2455 Add srd and srw 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 73daacbcd4 Add sim only divw 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago