This adds an output buffer to help with timing and allows the BRAMs
to actually pipeline.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This doesn't yet pipeline the block RAM, just generate a valid stall
signal so it's compatible with a pipelined master
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.
Fixing this improves the situation to one transfer every 2 cycles.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
(And rename it to mw_soc_memory).
This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt