cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
684 Commits
39 Branches
0 Tags
68 MiB
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '9046f5541d'
${ noResults }
Commit Graph

55 Commits (9046f5541d378e21ab8bff915bc9b9902fc033f1)

Author SHA1 Message Date
riktw 4ebd6fc1f7 Added support for building for Arty A7 boards 6 years ago
Olof Kindgren 12327034d6 Add and use plle2 primitive for nexys boards 6 years ago
Olof Kindgren b9bf19f912 Added synthesis target 
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.

To run synthesis only for a part, run

fusesoc run --target=synth --tool=vivado microwatt --part=<part>

where part is a valid Xilinx part such as xc7a100tcsg324-1
 6 years ago
Olof Kindgren 250d09ed2d Add Nexys Video support 6 years ago
Olof Kindgren 5e56b14125 Add FuseSoC core description file with Nexys A7 support 6 years ago