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microwatt
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caravel-mpw7-20221125
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trace-test
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litedram-update
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fpu-init
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2 Commits (8c028f26f1e7092ef34d1c7806328a4e2fa5fba7)

Author SHA1 Message Date
Paul Mackerras 3340d8aa9f mw_debug: Add support for reading GSPRs and writing memory 
This adds a "gpr" command for reading 1 or more GPRs/fast SPRs,
and a "mw" command for writing an 8-byte value to memory.  It also
adds an "icreset" command for resetting the instruction cache
and fixes the "creset" command to actually reset the core instead
of starting it.  The MSR is now printed along with the NIA in the
status information.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago
Benjamin Herrenschmidt fe275effeb New C based JTAG debug tool 
This works with both the sim socket and urjtag, and supports the
new core functions, loading a file in memory etc...

The code still needs a lot of cleanup and a help!

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago