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Commit Graph

5 Commits (819f8200905fa4ab7b6eafef8cb42606d6982bd9)

Author SHA1 Message Date
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt c97b080d8c Move wishbone arbiter out of the core 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt 8bfd6e5eae Use simulated UART in core test bench 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Anton Blanchard 1fa0b332ca micropython only requires 512kB of BRAM 
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 7 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 7 years ago