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caravel-mpw7-20221125
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litedram-update
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3 Commits (7ac167130c25acfe45e9425d9080f5ee0aec47f6)

Author SHA1 Message Date
Paul Mackerras 3e0888ae35 litesdcard: Update generated code 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 1 year ago
Paul Mackerras c1f23e7417 litesdcard: Regenerate verilog code with buffer direction controls 
This regenerates the verilog code from upstream litex plus a patch to
generate outputs from the litesdcard module for controlling
bidirectional buffers between the FPGA and SD card.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 2 years ago
Paul Mackerras 264e609fd4 litesdcard: Name targets by vendor.frequency, not just vendor 
In future we will want to support targets using the same vendor but
running at different clock frequencies.  Since the clock frequency is
a parameter to the gateware generation process, we now name the target
directories as "vendor.frequency", i.e., "xilinx.100e6" and
"lattice.48e6" rather than "xilinx" and "lattice".

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 2 years ago