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microwatt
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caravel-mpw7-20221125
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trace-test
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litedram-update
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fix-sdcard
fpu-init
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core_debug-init
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divider-init
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fpu-typo
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
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remove-potato-uart
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jtag-port-2
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nia-debug
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Commit Graph

6 Commits (7a4a9b6377cb04438ab02a25fe167b7e026b01fb)

Author SHA1 Message Date
Benjamin Herrenschmidt 1a63c39704 Make it possible to change wishbone address size 
All that needs to be changed now is the size in wishbone_types.vhdl
and the address decoder in soc.vhdl

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Anton Blanchard 1d5e8c2eb4 Reformat simple_ram_behavioural 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Anton Blanchard dce2e06f4c Don't send out X state from the memory behavioural 
Just send out all 1s.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5d82af5204 Silence some loadstore related debug 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago