Commit Graph

874 Commits (4c61a71a62e7c217699ff0597ee10cf3bfd18c1d)
 

Author SHA1 Message Date
Anton Blanchard 813f834012 Add CR hazard detection
To keep things simple we treat the CR as a single entity.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 58b348deae
Merge pull request #101 from antonblanchard/gpr-hazard-5-b
Add GPR hazard detection
5 years ago
Paul Mackerras c7025f9f28 divider: Add an output register
This puts the output of the divider through a register.  With the
addition of the logic to detect overflow, the combinatorial output
logic of the divider was becoming a critical path.  Adding the
output register adds a cycle to the latency of the divider but
helps make timing at 100MHz on the A7-100.

This also makes the valid, write_reg_enable and write_cr_enable
fields of the output be registered, which eliminates warnings
about register/latch pins with no clock.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Anton Blanchard bb65d0b899 Remove issue restrictions on a number of instructions
Anything that isn't a load or store and anything that doesn't read the
CR can go as soon as its inputs are ready.

While we could also allow SPR read/write and carry read/write, we plan
to change them to be read in decode2 and written in writeback soon and
they will need separate hazard detection to be added.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard bdc26b7527 Add GPR hazard detection
Check GPRs against any writers in the pipeline.

All instructions are still marked single in pipeline at
this stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard e4c98dce36
Merge pull request #100 from antonblanchard/gpr-hazard-5-a
Separate issue control into its own unit
5 years ago
Anton Blanchard f181bf31e2
Merge pull request #99 from paulusmack/logical
Logical
5 years ago
Anton Blanchard d5346d0abf Separate issue control into its own unit
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Paul Mackerras 4396eddc31 countzero: Add a testbench
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras e527e3a9b7 countzero: Reorganize to have fewer levels of logic and fewer LUTs
By using 4:1 multiplexers rather than 2:1, this cuts the number of
levels of multiplexing from 4 to 2 and also reduces the total number
of slice LUTs required.  Because we are now handling 4 bits at each
level, including the bottom level, the logic to do the priority
encoding can be factored out into a function that is used at each
level.

This rearranges the logic so that the encoding and selection of bits
is done whether or not the input operand is zero, and the if statement
testing whether the input is zero only affects what is assigned to
result.  With this we don't get the inferred latches and we can go
back to using signals rather than variables.

Also add some comments about what is being done.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Anton Blanchard 0a0fe03767
Merge pull request #98 from antonblanchard/fix-mod
mod* doesn't have an RC form
5 years ago
Anton Blanchard 10a990bba8 mod* doesn't have an RC form
The RC bit should be ignored for mod* instructions.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 56908edea2
Merge pull request #96 from antonblanchard/clk_gen_bypass-fix
Fix clk_gen_bypass
5 years ago
Anton Blanchard 6cdb8ca9f5 Fix clk_gen_bypass
clk_gen_bypass needed updating after the addition of CLK_INPUT_HZ and
CLK_OUTPUT_HZ.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 8530500a71
Merge pull request #94 from antonblanchard/icbi-nop
decode: Handle icbi
5 years ago
Anton Blanchard 854c93f970
Merge pull request #93 from antonblanchard/fifo-fix
Remove shared variable from fifo, and reformat
5 years ago
Anton Blanchard c41da84226 decode: Handle icbi
We will need a proper handler for icbi, but in the meantime treat it
as a nop.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 7aaed5abd5 fifo: Reformat
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard ad6c6790f9 fifo: Remove shared variable
The shared variable used for FIFO memory is not VHDL 2008 compliant.
I can't see why it needs to be a shared variable since reads and writes
update top and bottom synchronously, meaning they don't need same cycle
access to the FIFO memory.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard bd73c1753b
Merge pull request #92 from paulusmack/divider
Divider
5 years ago
Anton Blanchard 625eb0175f
Merge pull request #91 from tgingold/gpr-file-fix
Fix register file size (there are 32 gprs).
5 years ago
Paul Mackerras d4f51e08c8 divider: Return 0 for invalid and overflow cases, like P9 does
This adds logic to detect the cases where the quotient of the
division overflows the range of the output representation, and
return all zeroes in those cases, which is what POWER9 does.
To do this, we extend the dividend register by 1 bit and we do
an extra step in the division process to get a 2^64 bit of the
quotient, which ends up in the 'overflow' signal.  This catches all
the cases where dividend >= 2^64 * divisor, including the case
where divisor = 0, and the divde/divdeu cases where |RA| >= |RB|.

Then, in the output stage, we also check that the result fits in
the representable range, which depends on whether the division is
a signed division or not, and whether it is a 32-bit or 64-bit
division.  If dividend >= 2^64 or the result doesn't fit in the
representable range, write_data is set to 0 and write_cr_data to
0x20000000 (i.e. cr0.eq = 1).

POWER9 sets the top 32 bits of the result to zero for 32-bit signed
divisions, and sets CR0 when RC=1 according to the 64-bit value
(i.e. CR0.LT is always 0 for 32-bit signed divisions, even if the
32-bit result is negative).  However, modsw with a negative result
sets the top 32 bits to all 1s.  We follow suit.

This updates divider_tb to check the invalid cases as well as the
valid case.

This also fixes a small bug where the reset signal for the divider
was driven from rst when it should have been driven from core_rst.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras 5c0ba90722 decode2: Fix 32-bit flag passed to divider
Previously the 32-bit flag passed to the divider was always wrong;
this fixes it.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Tristan Gingold 0169d48ee6 Fix register file size (there are 32 gprs). 5 years ago
Anton Blanchard bbb1a3610c
Merge pull request #84 from classilla/master
Add logo
5 years ago
Anton Blanchard 460447a31b
Merge pull request #89 from mikey/gitignore
Update gitignore for new test bench build files
5 years ago
Anton Blanchard 23f8702e68
Merge pull request #90 from antonblanchard/newcrf-inferred-latch
Don't infer latch for newcrf
5 years ago
Anton Blanchard 57b7f1ed71 Don't infer latch for newcrf
Always initialize newcrf to avoid inferring a latch.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Michael Neuling 1edc4aa004 Update gitignore for new test bench build files
Just ignore all *_tb files

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Anton Blanchard f76b5f9ea2
Merge pull request #87 from antonblanchard/cmod-a7-freq
Fix cmod-a7 frequency
5 years ago
Anton Blanchard 9b8c094cf6 Fix cmod-a7 frequency
The cmod-a7 is ignoring the clk_frequency parameter and running at
100 MHz. Fix it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 16ca868909
Merge pull request #86 from antonblanchard/outstanding-range
Limit outstanding range
5 years ago
Anton Blanchard 938b453501
Merge pull request #85 from antonblanchard/leadingzeroes-fix
Fix count-leading/trailing-zeroes
5 years ago
Anton Blanchard e54db5b496
Merge pull request #79 from deece/uart_address
Tighten UART address
5 years ago
Anton Blanchard 4016f69e70 Limit outstanding range
outstanding can only ever be -1 to 2 at the moment (0 or 1 on a
rising clock edge). Vivado is synthesizing a much wider adder
which is silly. Constrain it with a range statement. This should
be good for timing and saves us about 85 LUTs.

This will get relaxed when we add more pipelining, but only by a
few bits.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 1b559aee31 Fix count-leading/trailing-zeroes
The current code simulates correctly, but produces miscompares when synthesized
onto an FPGA. On closer inspection GHDL synthesis complains about inferred
latches and there does seem to be issues.

Convert it to variables that are always initialized to zero at the start of the
process.

Fixes: 24a4a796ce ("execute: Consolidate count-leading/trailing-zeroes implementations")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Cameron Kaiser 07d3c8e4de Add logo to README.md
Signed-off-by: Cameron Kaiser <classilla@floodgap.com>
5 years ago
Cameron Kaiser 0cb0f78777 Add title image
Signed-off-by: Cameron Kaiser <classilla@floodgap.com>
5 years ago
Anton Blanchard 3c6e66dc96
Merge pull request #83 from paulusmack/logical
execute: Consolidate count-leading/trailing-zeroes implementations
5 years ago
Anton Blanchard 4b7b702e01
Merge pull request #81 from antonblanchard/logical
Consolidate logical instructions
5 years ago
Anton Blanchard 5dff75219c
Merge pull request #82 from antonblanchard/icache-set-assoc
A new set associative icache from Ben
5 years ago
Paul Mackerras 24a4a796ce execute: Consolidate count-leading/trailing-zeroes implementations
This adds combinatorial logic that does 32-bit and 64-bit count
leading and trailing zeroes in one unit, and consolidates the
four instructions under a single OP_CNTZ opcode.

This saves 84 slice LUTs on the Arty A7-100.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Anton Blanchard b8fb721b81 Consolidate logical instructions
Consolidate and/andc/nand, or/orc/nor and xor/eqv, using a common
invert on the input and output. This saves us about 200 LUTs.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Alastair D'Silva ccd52bf6f2 Tighten UART address
The current scheme has UART0 repeating throughout the UART address range.

This patch tightens the address checking so that it only occurs once.

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
5 years ago
Benjamin Herrenschmidt b56b46b7d1 icache: Set associative icache
This adds support for set associativity to the icache. It can still
be direct mapped by setting NUM_WAYS to 1.

The replacement policy uses a simple tree-PLRU for each set.

This is only lightly tested, tests pass but I have to double check
that we are using the ways effectively and not creating duplicates.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 004eb074c9 plru: Add a simple PLRU module
Tested in sim only for now

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt e1cf44cec8 fetch2: Remove blank line
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt d40c1c1a25 icache: Use narrower block RAMs
We only ever access the cache memory for at most the wishbone bus
width at a time. So having the BRAMs organized as a cache-line-wide
port is a waste of resources.

Instead, use a wishbone-wide memory and store a line as consecutive
rows in the BRAM.

This significantly improves BRAM usage in the FPGA as we can now use
more rows in the BRAM blocks. It also saves a few LUTs and muxes.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt d415e5544a fetch/icache: Fit icache in BRAM
The goal is to have the icache fit in BRAM by latching the output
into a register. In order to avoid timing issues , we need to give
the BRAM a full cycle on reads, and thus we souce the BRAM address
directly from fetch1 latched NIA.

(Note: This will be problematic if/when we want to hash the address,
we'll probably be better off having fetch1 latch a fully hashed address
along with the normal one, so the icache can use the former to address
the BRAM and pass the latter along)

One difficulty is that we cannot really stall the icache without adding
more combo logic that would break the "one full cycle" BRAM model. This
means that on stalls from decode, by the time we stall fetch1, it has
already gone to the next address, which the icache is already latching.

We work around this by having a "stash" buffer in fetch2 that will stash
away the icache output on a stall, and override the output of the icache
with the content of the stash buffer when unstalling.

This requires a rewrite of the stop/step debug logic as well. We now
do most of the hard work in fetch1 which makes more sense.

Note: Vivado is still not inferring an built-in output register for the
BRAMs. I don't want to add another cycle... I don't fully understand why
it wouldn't be able to treat current_row as such but clearly it won't. At
least the timing seems good enough now for 100Mhz, possibly more.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 3589f92d5a fetch1: Simplify a bit
There is no need to have two different state records

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago