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caravel-mpw7-20221125
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2 Commits (49b332e17f9ff2ece65a1c83b8d1b3edc12e33f2)

Author SHA1 Message Date
Anton Blanchard 5249d633cf Move register stage from after RAM to before RAM 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 8ecb30da05 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago