Commit Graph

408 Commits (471c7e2197a998bddb631f7ffdec921efa3437c4)
 

Author SHA1 Message Date
Paul Mackerras c9e92483b8 decode: Push mtspr/mfspr register decoding down into execute1
Instead of doing mfctr, mflr, mftb, mtctr, mtlr as separate ops,
just pass down mfspr and mtspr ops with the spr number and let
execute1 decode which SPR we're addressing.  This will help reduce
the number of instruction bits decode1 needs to look at.

In fact we now pass down the whole instruction from decode2 to
execute1.  We will need more bits of the instruction in future,
and the tools should just optimize away any that we don't end
up using.  Since the 'aa' bit was just a copy of an instruction
bit, we can now remove it from the record.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Benjamin Herrenschmidt 3e6f656a90 Add MCRF instruction
Hopefully it's not too timing catastrophic. The variable newcrf will
be handy for the other CR ops when we implement them I suspect.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 554ae88540 Implement absolute branches
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Anton Blanchard 4174cd8e93
Merge pull request #77 from antonblanchard/timing
A number of timing fixes
4 years ago
Anton Blanchard 4a9a9df4dd
Merge pull request #76 from antonblanchard/misc
Some misc updates
4 years ago
Benjamin Herrenschmidt 9961d70dfb Improve PLL/MMCM clocks configuration
We can now pass both the input clock and target clock frequency
via generics. Add support for both 50Mhz and 100Mhz target freqs
for both cases.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 5f28109957 Don't reset JTAG request register asynchronously
There's no point and it causes Vivado to spew a pile of warnings

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 48e6e719d3 Multiply needs to be 16 stages to fix all timing issues
This seems dependent on the FPGA type/size, so we should probably
make it a toplevel generic, but for now this helps on the
Arty A7-35

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras 9789d258fb loadstore2: Do data formatting after a register stage
This moves the data formatting for read data to after a register,
instead of before, in order to improve timing.  The data formatting
is now effectively combinational logic on the input side of the
writeback stage.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Benjamin Herrenschmidt 492bf06740 corefile: Remove duplicate wishbone_debug_master
It's both in core and soc, it should only be in the latter

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt ab5c6ab9ac fpga: Arty A7's don't need multiple filesets
the XDC is identical between variants, so is the fileset

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 80a0e7fcf3 execute1: simplify flush_out
It's always set when f_out.redirect is set, so may as well set it once
at the end. It's all combo from the register.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 8b55fc4d9e Reformat fetch2
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 41a4eb8271 Move fetch2 <-> icache definitions
To a more logical place before decode related ones

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 79b64baefc Remove unused pipe_stop in Fetch1ToFetch2Type
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 79b0b9a046 Fix PLL reset signal name in toplevel
It shouldn't have a _n suffix, it's active positive.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 8af2b004c3 Simplify fetch1
Do the +4 in a single place. This shouldn't cause any difference
in behaviour as these are sequential variable assignments.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 3a6fcc09d4 Reformat fetch1
No code change

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 586abb70a0 Update dependency
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Anton Blanchard feb8ee7149
Merge pull request #75 from paulusmack/master
fpga: Add definitions for Arty A7-100 board
4 years ago
Anton Blanchard 555802d996
Merge pull request #74 from paulusmack/divider
Divider
4 years ago
Paul Mackerras 1158c81500 fpga: Add definitions for Arty A7-100 board
These are a copy of the A7-35 definitions with 35 changed to 100.
The A7-100 uses the same .xdc file (arty_a7-35.xdc) as the A7-35
since the only difference between the two is the FPGA part; the
hardware and connections on the two boards are identical.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 25b9450475 divider: Do absolute-value ops in divider instead of decode
This moves the negation of negative operands for signed divide and
modulus operations out of the decode2 stage and into the divider.
If either of the operands for a signed divide or modulus operation
is negative, the divider now takes an extra cycle to negate the
operands that are negative.

The interface to the divider now has an 'is_signed' signal rather
than a 'neg_result' signal, and the dividend and divisor can be
negative, so divider_tb had to be updated for the new interface.

The reason for doing this is that one of the worst timing violations
on the Arty A7-100 at 100MHz involved the carry chain in the adders
that did the negation of the dividend and divisor in the decode stage.
Moving the negations to a separate cycle fixes that and also seems to
reduce the total number of slice LUTs used.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras e6536d4b8b divider: Always compute result/sresult/d_out.write_reg_data
These are intended to be combinatorial.  The previous code was giving
warnings in vivado about registers/latches with no clock defined.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Anton Blanchard ad040601e6
Merge pull request #73 from antonblanchard/remove-divide-patch
Remove gcc software divide patch
4 years ago
Anton Blanchard c8328cdf84 Remove gcc software divide patch
We have a divider, thanks to Paul.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 82fe8dc6e2
Merge pull request #72 from antonblanchard/build-error
Fix build issue in dmi_dtm_dummy.vhdl
4 years ago
Anton Blanchard a9e5fe78fb
Merge pull request #71 from antonblanchard/dependencies
Update Makefile dependencies
4 years ago
Anton Blanchard 8102e7863b Fix build issue in dmi_dtm_dummy.vhdl
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 26f70264b3 Update Makefile dependencies
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard b57325ce29 Merge branch 'divider' of https://github.com/paulusmack/microwatt 4 years ago
Anton Blanchard cd4da50650
Merge pull request #70 from antonblanchard/badly-named-carry
Rename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE
4 years ago
Anton Blanchard 5a6f8d26d1 Rename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE
These were somewhat badly named.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard ba783fddd5
Merge pull request #69 from antonblanchard/debug-module
Merge debug module patches
4 years ago
Anton Blanchard 6cae10eebd Terminate test on illegal instruction
This gets the CI going again, but we will want to fix the test
harness since it's useful to be able to debug the core after it
executes an illegal instruction.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard 8c5dcc8c4c Fix ghdl error
I'm seeing an issue on my version of ghdl:

  core.vhdl:137:24:error: actual expression must be globally static

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Anton Blanchard d82f4c18b6 Add core_debug.vhdl to fusesoc configs
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
4 years ago
Paul Mackerras a01ffaeb64 Speed up the divider a little
This looks for cases where the next 8 bits of the quotient are obviously
going to be zero, because the top 72 bits of the 128-bit dividend
register are all zero.  In those cases we shift 8 zero bits into the
quotient and increase count by 8.  We only do this if count < 56.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Paul Mackerras d5bc6c8824 Add a divider unit and a testbench for it
This adds a divider unit, connected to the core in much the same way
that the multiplier unit is connected.  The division algorithm is
very simple-minded, taking 64 clock cycles for any division (even
32-bit division instructions).

The decoding is simplified by making use of regularities in the
instruction encoding for div* and mod* instructions.  Instead of
having PPC_* encodings from the first-stage decoder for each of the
different div* and mod* instructions, we now just have PPC_DIV and
PPC_MOD, and the inputs to the divider that indicate what sort of
division operation to do are derived from instruction word bits.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
Benjamin Herrenschmidt 42d802bed0 Add distclean to Makefile
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt fe275effeb New C based JTAG debug tool
This works with both the sim socket and urjtag, and supports the
new core functions, loading a file in memory etc...

The code still needs a lot of cleanup and a help!

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 98f0994698 Add core debug module
This module adds some simple core controls:

  reset, stop, start, step

along with icache clear and reading the NIA and core
status bits

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org
5 years ago
Benjamin Herrenschmidt 554b753172 Add jtag support in simulation via a socket
This adds a local socket that can be used to communicate with
the debug tool (which will be committed separately) and generates
the JTAG signals.

We generate the low level JTAG signals, thus directly driving the
simulated BSCANE2, and the Xilinx DTM

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt ad14a41d80 Add DMI address decoder
And prepare signals for core DMI support

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt b46f81fae4 Wishbone debug module
This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
This adds a simple bus that can be mastered from an external
system via JTAG, which will be used to hookup various debug
modules.

It's loosely based on the RiscV model (hence the DMI name).

The module currently only supports hooking up to a Xilinx BSCANE2
but it shouldn't be too hard to adapt it to support different TAPs
if necessary.

The JTAG protocol proper is not exactly the RiscV one at this point,
though I might still change it.

This comes with some sim variants of Xilinx BSCANE2 and BUFG and a
test bench.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 1206dfe18c Use a 3 way WB arbiter and cleanup fpga toplevel
The 3rd master is currently unused, it will host the WB debug module.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Anton Blanchard 6571b13308
Merge pull request #66 from antonblanchard/reformat-4
More reformatting
5 years ago
Anton Blanchard 7e7010c304 Reformat crhelpers, and remove some stale code
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard ae42370d24 Reformat helpers
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago