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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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core_debug-init
icache-unused-sig
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divider-init
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fpu-typo
less-fpga-init
caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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jtag-port-2
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nia-debug
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3 Commits (471c7e2197a998bddb631f7ffdec921efa3437c4)

Author SHA1 Message Date
Anton Blanchard 471c7e2197 Consolidate VHPI code 
We had many copies of the VHPI marshalling/unmarshalling code.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Benjamin Herrenschmidt a2969fa298 debug/sim: Make connect/disconnect messages quieter 
Those don't need to go to stderr, send them to stdout instead

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt 554b753172 Add jtag support in simulation via a socket 
This adds a local socket that can be used to communicate with
the debug tool (which will be committed separately) and generates
the JTAG signals.

We generate the low level JTAG signals, thus directly driving the
simulated BSCANE2, and the Xilinx DTM

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago