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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
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unused-sig
divider-init
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fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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jtag-port-2
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nia-debug
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4 Commits (374f4c536d3c4dd8051a139b8e25691ba82e35b7)

Author SHA1 Message Date
Anton Blanchard 813f834012 Add CR hazard detection 
To keep things simple we treat the CR as a single entity.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard bb65d0b899 Remove issue restrictions on a number of instructions 
Anything that isn't a load or store and anything that doesn't read the
CR can go as soon as its inputs are ready.

While we could also allow SPR read/write and carry read/write, we plan
to change them to be read in decode2 and written in writeback soon and
they will need separate hazard detection to be added.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard bdc26b7527 Add GPR hazard detection 
Check GPRs against any writers in the pipeline.

All instructions are still marked single in pipeline at
this stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard d5346d0abf Separate issue control into its own unit 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago