cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
1,467 Commits
39 Branches
0 Tags
68 MiB
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '34cf092bf6'
${ noResults }
Commit Graph

2 Commits (34cf092bf6da6e1156c4fa8d9b20d02d0e758e76)

Author SHA1 Message Date
Benjamin Herrenschmidt d299ea925e Bundle the uart16550 core file 
We already carry the UART verilog source, so we may as well use it
instead of requiring fusesoc to import it from its library

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 3 years ago
Michael Neuling aae45583d7 Add uart16550 files from fusesoc 
These are needed for synthesis that doesn't use fusesoc natively.

These were pulled in via 'fusesoc fetch ::uart16550:1.5.5-r1'

Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago