Commit Graph

2 Commits (21ab36a0c0cc05501d036a160f3002d21b7cd9cd)

Author SHA1 Message Date
Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <>
Signed-off-by: Michael Neuling <>
2 years ago
Boris Shingarov 679c547e5f fpga: Add support for Genesys2
Signed-off-by: Boris Shingarov <>
4 years ago