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caravel-mpw7-20221125
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2 Commits (2083bc3ed0302c9c9a4866b6dc86b7d4496abcd5)

Author SHA1 Message Date
Anton Blanchard ace41e5153 ASIC: Reduce multiplier from 4 to 2 cycles 
Our sky130 gate level multiply/adder now makes timing with a single
register stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 8ecb30da05 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago