Commit Graph

9 Commits (11c5ac68e8e8ad17e846aa32ba832251be4bb92c)

Author SHA1 Message Date
Anton Blanchard c7ef75b55c Forgot multiply.vhdl
Anton Blanchard e70d7f0a60 Make caches 1 way
Anton Blanchard 7da4977028 Disable FPU
Anton Blanchard 1383bbb8be Add GPIOs
Anton Blanchard 46a85cb274 Add asic alternate reset address
Anton Blanchard 4e9001ba19 Hook up JTAG to asic top level
Anton Blanchard 18503732d7 Add ASIC target
Anton Blanchard 5ac715d932 Fix multiplier behavioural
Anton Blanchard 537a0aac1d Add arrays for ASIC flow
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>