Commit Graph

2 Commits (0cb0f7877744851f2efc0ddcb45a031603173da6)

Author SHA1 Message Date
Michael Neuling 83d773090e Fix verific script with new VHDL files
This really needs to be auto generated, but here we are.

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Michael Neuling 4d5abfb430 Remove dynamic ranges from code
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.

Also add basic script to run verific and generate verilog.

1. https://www.verific.com/

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago