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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
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boxarty-20211011
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orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
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caravel-20210105
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Commit Graph

3 Commits (05bbbf0772f5f05677f62574583fd3a105db12ac)

Author SHA1 Message Date
Benjamin Herrenschmidt 7192ee825f litedram: Improve dram_tb error output 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 4 years ago
Benjamin Herrenschmidt a93d9e77c9 litedram: Remove remnants of riscv-inits 
We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 6828e93113 litedram: Test bench 
The test bench test simple access forms for now, it's a starting point
but it already helped find/fix a bug.

Includes a litedram update to be able to operate the sim model without
inits.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago